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Embedded Flash/EEPROM for Smart IoT, June 2017
(Single Poly & Split-Gate, Double Poly, Floating Gate & Charge Trapping)

Embedded non-volatile memory in MCUs controlling the Smart Internet of Things needs attributes different from high volume standalone Flash and EEPROM. These embedded Flash and EEPROM must be low cost and producible in standard CMOS processes. Cost adders to the process must be minimized while the electrical characteristics and reliability must be adequate for the various IoT applications. These applications require various memory capacities from a few bits to many Mbits. They require electrical characteristics ranging from very low voltage operation in energy harvesting sensors to very high temperature high performance automotive applications. While the performance must be adequate, the cost must be minimized.
Several of these embedded NVM are available as commercial macros at various foundries. 110+ pages.

Embedded Flash/EEPROM for Smart IoT, June 2017
(Single Poly & Split-Gate, Double Poly, Floating Gate & Charge Trapping)

Table of Contents

1.0 Introduction to eFlash/eEEPROM for Smart IoT

2.0 Summary of Application Requirements for Embedded Flash in IoT

3.0 Single Poly Floating Gate eFlash/EEPROM Cells

  • 3.1 Early Single Polysilicon Floating Gate EEPROMS
  • 3.2 Recent Single Poly eFLash in Standard CMOS for RFID Type Applications
    • 3.2.1 Single Poly eFlash in Standard CMOS with no Mask or Process adders (Genusion)
    • 3.2.2 RFID TAG IC in 180 nm CMOS with 4kbit EEPROM (eSilicon)
    • 3.2.3 Low Power Single Polysilicon eFlash for Use in an RFID Tag (Ben-Gurion U, TowerJazz)
    • 3.2.4 Embedded Memory for using in RFID Tags (eMemory)
  • 3.3 Other CMOS Compatible Single Poly Embedded NVM
    • 3.3.1 Data Retention Mechanisms of Logic Embedded NVM in MTP Applications(TSMC)
    • 3.3.2 Single Poly CMOS Half-MOS MTP EEPROM Cell (U. of Brescia, STMicroelectronics)
    • 3.3.3 Simulation Model for Single Poly EEPROM cell (Nat. U. of Defense Tech. China)
    • 3.3.4 3T EEPROM Devices in Conventional CMOS Logic (FlashSilicon)
    • 3.3.5 Scalable Single Poly eEEPROM with W CG in CMOS Logic Process (NTHU)
    • 3.3.6 Single Poly EEPROM in CMOS for Medium Density Applications (U. Brescia)
  • 3.4 Single Polysilicon eNVM in High Voltage CMOS
    • 3.4.1 Select Gate Lateral Coupling(SGLC) Single Poly eNVM in HVCMOS (SK Hynix)
    • 3.4.2 Byte-Alterable, HVCMOS Logic Compatible, 90 nm, 3T Cell EEPROM (Genusion)
  • 3.5 eFlash Cells Using Multiple Single Polysilicon CMOS Logic Transistors
    • 3.5.1 Single Poly 5T Logic Compatible Floating Gate eFlash Memory (U. of Minnesota)
    • 3.5.2 N-Channel and P-Channel Single Poly FG eFlash Devices (U. of Minnesota)
    • 3.5.3 5T Single Poly eFlash Technology in Conventional CMOS Logic (U. of Minnesota)
    • 3.5.4 Bit-by-Bit ReWritable 6T eFlash Cell in Logic Process (U. of Minnesota)
    • 3.5.5 5T Single Poly eFlash in Conventional CMOS Logic (U. of Minnesota)
    • 3.5.6 2T Embedded MTP Memory Cell in Standard CMOS Technology

4.0 Split Gate Technology for Floating Gate Embedded Flash

  • 4.1 Overview of Early Split-Gate Embedded Flash Technology
  • 4.2 A 65 nm Embedded Split-Gate FG Flash Memory Technology (TSMC)
  • 4.3 Test Structure Using a Split-gate Flash Cell Configuration Element (Microchip/SST)
  • 4.4 Split Gate eFlash for MCU in 55 nm 5M CMOS LP Process (TSMC)
  • 4.5 Fast Random Read Access eFlash Macro for Mobile Processors (NTHU, ShouU, TSMC)
  • 4.6 Reduction of Program Induced Degradation for Advanced Split Gate Flash (SST)
  • 4.7 45 nm 1.5T Split-Gate eFlash Cell for Smart Phones (Samsung)
  • 4.8 Binary Code Inversion Method for Low Current eFlash Sense Amplifier (KAIST)
  • 4.9 Program Disturb in 3rd Generation 90 nm Split-Gate SST Memory (STT/Microchip
  • 4.10 2-bit/cell Split Gate Flash with Program Disturb Immunity (CAS, Huahong Grace)
  • 4.11 Peripheral Circuits for Split-Gate NOR eFlash (CAS, GSMC, Shanghai Huahong)
  • 4.12 Production SPICE Model for 55 nm SplitGate eFlash (CEA-LETI, Microchip)
  • 4.13 55 ns Split-Gate Flash Array for Automotive and for Smart Cards (SST/Microchip)
  • 4.14 Twin-Bit-eNVM with Virtual Ground Architecture(CAS, Shanghai Huahong, GSMC)
  • 4.15 200KB Embedded 1.5V EEPROM in 90 nm EEPROM Technology
  • 4.16 Effect of Radiation & Stress Degradation on S-G NOR Flash (NAVSEA Crane)
  • 4.17 Properties of Several Embedded NVM used in MCU (Microchip Tech/SST)
  • 4.18 Optimizing Programning and Endurance of 3rd Generation SG-MONOS Cell
  • 4.19 2nd Generation 45 nm Split Gate eFlash Scaled to 28 nm Technology (Samsung)
  • 4.20 25 nm 16Mb FG Flash in 40 nm Shrink CMOS (GlobalFoundries & Singapore UT)
  • 4.21 Program Disturb Mechanisms in ESF3 Cell (Microchip/SST)

5.0 Stacked Flash and Processor TSV Integration

6.0 OTP/MTP Embedded Flash Cells and Fuses

  • 6.1 Using HV & Standard CMOS IP Circuitry for a low cost eMTP (Nat.Chung.Hsing U)
  • 6.2 One-Time-Programmable (OTP) Cells for 16 nm FinFET Technology (Sidense)
  • 6.3 Fully Logic Compatible OTP Cell for Fuse Using Dielectric Breakdown (NCTU, UMC)
  • 6.4 Multiple Time Programmable NVM for HKMG Technology (IBM,UCLA)
  • 6.5 Embedded Flash with Reverse Drain-Source Cell (SMIC)

7.0 Stacked Gate (Flotox) Flash

  • 7.1 Embedded eFLOTOX Flash on Low Power 55 nm Logic DDC Process (Fuitsu)
  • 7.2 Stacked Gate Embedded Flash FG Cell in 65 nm LP-CMOS (Lattice Semi., Fujitsu)
  • 7.3 Classification Method for Erratic Bits in Automotive eFlash(U.de Studi di Ferrar, Infineon)
  • 7.4 Integrating Double Poly NVM in Base Line CMOS (ON Semiconductor)
  • 7.5 High Voltage Process Floating Gate Stacked eFlash

8.0 Novel Embedded Flash Memory

  • 8.1 TaN Antifuse Electromechanical OTP Antifuse for eNVM (A*STAR, U. of Singapore)
  • 8.2 4kB Fast NV Nanogap Memory (FEAT Research Institute, NIAIST)

9.0 Charge Trapping eFlash:

  • 9.1 Overview of Embedded Charge Trapping Memory
  • 9.2 Early Embedded MONOS Memory Devices
  • 9.3 Embedded MONOS Flash MCU (Renesas)
    • 9.3.1 Embedded 40 nm MONOS Flash-based MCU Platform (Renesas, TSMC)
    • 9.3.2 eFlash MONOS MCU in 28 nm Technology (Renesas)
    • 9.3.3 90nm 1T-MONOS eFlash Macro for High Performance Automotive (Renesas)
    • 9.3.4 FinFET SG- MONOS For Advanced Automotive Applications
  • 9.4 Embedded Charge Trapping Flash (Cypress)
    • 9.4.1 Embedded CT Flash Based on Production MirrorBit Cell (Spansion/now Cypress)
    • 9.4.2 Low Voltage, Low Cost SONOS Memory Technology (Cypress, UMC)
    • 9.4.3 Functioning 55 nm eSONOS for Smart Cards and IoT (Cypress, Shanghai Huali)
    • 9.4.4 Charge Trapping Flash Memory Devices (Spansion/ now Cypress)
    • 9.4.5 40 nm SONOS eFLash IP to Foundry for MCU, IoT and Wearables (Cypress, UMC)
  • 9.5 2T SONOS Embedded NVM (Hynix)
    • 9.5.1 2T SONOS NVM in HVCMOS for MCU for Touch Screens (SK Hynix, Wingcore)
    • 9.5.2 P/E Characteristics of 2T SONOS NVM Cell (SK Hynix, Sogang U.)
  • 9.6 On-Chip Recovery for Self-Aligned Nitride Logic NVM (NTHU, TSMC)
  • 9.7 Dynamic Programming Method for Embedded SONOS Flash Memory(eMemory)
  • 9.8 Charge Trap eFlash for Low Energy Applications (ST-Micro, A-Marseille U.)
  • 9.9 Blocking and Tunnel Oxide of DT BE-SONOS Performance (Macronix, NCTU)

10.0 Development of Embedded Charge Trap Memories

  • 10.1 Comparison of SONOS and NC Gates in a Vertical GAA NV Memory (Jadavpur U.)
  • 10.2 Nitrided La2O3 Charge Trapping MONOS Device (U.of Hong Kong, HK, U.of S&T)
  • 10.3 Multi-Bit Schottky Barrier Charge Trap NV Memory Cells (NCNU,TSMC,NTHU)
  • 10.4 Charge Trapping MAHOS NV Memory with SiGE Buried Channel (NTHU, ITRI)
  • 10.5 Method for Shortening Transient Vth Shift After Erase in CT Flash (KAIST, Hynix)
  • 10.6 CMOS Process Compatible ZnO Charge Trap MONOS NV Memory (Korea Univ)
  • 10.7 CT NVM with IGZO Channel & ZnO CT Layer (Kyung-HeeU. ,E&T Res. Inst)
  • 10.8 3D Fin-FET MANOS Flash with Al2O3 Blocking Layer (AIST, NIMS)
  • 10.9 Trapping Properties of HfO2 CT eNVM (U. of Udine, MDM Lab IMM-CNR)
  • 10.10 MOHOS NV Memory Device using a ZrO2 Trapping Layer (Chang Gung U)
  • 10.11 eNVM Using Trapped Electrons in CMOS High-k Gate Dielectric (IBM, UCLA)

11.0 Split Gate CT eFlash Replacing Nitride with Nanocrystal Storage (Freescale)

  • 11.1 128KB Split Gate CT eFlash (NXP/Freescale)
  • 11.2 32-bit MCU Family with Embedded NC Memory Storage (NXP/ Free Scale)
  • 11.3 Metal Nano-Particle Junctionless FET

12.0 Foundry eFlash in Conventional CMOS Logic

  • 12.1 Chart of Commercial eFlash Using in Foundries
  • 12.2 Summary of Various Commercial eFLash IP

Bibliography

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