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Trends in Embedded DRAM Technology, August 2015
(Gain Cell, 1T1C Cell, Sub-Systems, 1T-DRAM, FeDRAM)

Embedded DRAMs include: Gain cell eDRAMs, conventional 1T1C eDRAMs, Capacitorless floating body 1T eDRAMs, Ferroelectric eDRAMs and other novel eDRAMs. Gain cell eDRAMs use logic transistors for cells that are smaller than an SRAM and very low cost since they are fully compatible with scaled logic technologies. Reads are non-destructive. Improvements in retention, which reduce refresh energy, are being studied for gain cell eDRAMs along with improvements in read access time at low voltage.

1T1C eDRAM macros in FinFET/Trigate technology are being embedded in advanced processors. These macros have deep trench capacitors or stacked high-k MIM capacitors and are used in lower level cache for high density and in graphics applications for high bandwidth. Circuits and circuit techniques for improved performance, enhanced reliability, and on-chip test are being developed for use with 1T1C eDRAM macros.

Capacitorless (floating body) 1T eDRAMs made in FinFET/Trigate technology as well as in planar CMOS have small cells and tend to scale with the technology. 1T eDRAM cells with steep subthreshold swing have potential for lower power with supply voltage scaling below 1V. New 1T eDRAM cell structures are proposed.

4F2 1T FeDRAMs using ferroelectric HfO2 gate oxide have a simple cell, non-destructive read, long retention, reduced power and compatibility with CMOS logic. In addition, various novel eDRAM cells are being researched.

85+ pages.

Trends in Embedded DRAM Technology, August 2015

Table of Contents

Executive Summary

1. Overview of Embedded DRAMs

  • 1.1 Overview of Report
  • 1.2 Comparison of Various Embedded Memories and Their Properties

2.0 Gain Cell eDRAMs

  • 2.1 Overview of Gain Cell eDRAMs
  • 2.2 Single Supply Low Voltage and Power 3T Gain Cell (Bar-Ilan U, EPFL)
  • 2.3 Gain Cell Architecture with Differential Pair and Current Stop (Purdue U.)
  • 2.4 2T eDRAM Gain Cell with Enhanced Data Retention Time (Fudan U.)
  • 2.5 Analysis for 32 nm 3T1D DRAM Cell (JSS Acad. of Tech. Ed. India)
  • 2.6 Non-Volatile 180 nm 4x4 4T1D DRAM test cell (Saintgits Coll. of Eng, India)
  • 2.7 4T Gain Cell eDRAM with Internal Feedback for Low Retention Power (Ben-GurionU)
  • 2.8 2T eDRAM with Body-Toggle and Write-Back Schemes (Kyungpook Nat. U.)
  • 2.9 Adaptive Refresh Timing of Gain Cell eDRAM (EPFL, Ben-Gunon U. Bar-Ilan U.)

2.10 2T1D eDRAM with Local Voltage Sensing (Broadcom, Samsung, U. of Minnesota)

3.0 High Performance 1T1C eDRAMs

  • 3.1 Overview of High Performance 1T1C eDRAM Cells
  • 3.2 eDRAM Macro in 14 nm Technology (IBM)
  • 3.2.1 Mb eDRAM Macro in 14 nm Technology with 1 ns Access Time (IBM)
  • 3.2.2 14 nm SOI FinFET CMOS Technology with Deep Trench eDRAM (IBM)
  • 3.2.3 22 nm eDRAM Cell with Deep Trench Capacitor (IBM)
  • 3.2.4 32 nm Deep Trench eDRAM with HKMG nFET (IBM)
  • 3.3 eDRAM in 22 nm CMOS Logic Technology (Intel)
  • 3.3.1 eDRAM with MIM Capacitor in 22 nm CMOS Logic Technology (Intel)
  • 3.3.2 2nd Gen. 22 nm Tri-Gate CMOS eDRAM with 4X Lower Self Refresh Power (Intel)
  • 3.3.3 Integration of 3D MIM Capacitor and Access Transistor (Intel)
  • 3.3.4 1Gb 2 GHz eDRAM in 22 nm Tri-Gate CMOS (Intel)
  • 3.3.5 22 nm Tri-Gate CMOS eDRAM Retention Time Optimization (Intel)
  • 3.3.6 22 nm COB eDRAM Cell Using Trigate Transistor (Intel)
  • 3.4 Noise Analysis in eDRAM MIM Capacitors and 1T FBRAM (IMEC, Micron, U. Messina)
  • 3.5 Using FinFET Technology for eDRAM Cells (U. Politec. Catalunya)
  • 3.6 Model for Retention Time in Fast eDRAM Arrays (U. of South Florida)
  • 3.7 SrRuO2/SrTiO3/SrRuO2 Capacitors in DRAM Applications (TU Munich, IWE-RWTH)
  • 3.8 Trench Multiplication Process Using Sacrificial SiGe Epitaxial Layer (Infineon)
  • 3.9 Metal Assisted Chemical Etching for Vertical 3D Trenches (Georgia IT)
  • 3.10 Modeling Retention Time for Fast eDRAMs (U. of South Florida)
  • 3.11 Low Power, Fast DRAM Readout Method (Port Said U.)

4.0 eDRAMs in Systems and Subsystems : Reliability, Test, Debug, ECC, Repair

  • 4.1 Overview of eDRAM in System and Subsystems
  • 4.2 Software Wear Leveling for Hybrid PCM+DRAM (Okla.SU., City U. of HK, ChongqingU)
  • 4.3 Software-Based Test and Diagnosis of SoCs with eDRAM (Duke U.)
  • 4.4 eDRAM Memory and Subsystems of IBM "Power8" Processor (IBM)
  • 4.4.1 22nm SOI Technology with Trench eDRAM in Power8 Processor (IBM)
  • 4.4.2 Cache and Memory Subsystems of IBM "Power8" Processor (IBM)
  • 4.4.3 Circuit Design and Energy optimization of the IBM "Power8" processor (IBM)
  • 4.4.4 22 nm SOI Trench eDRAM and SRAM in 12-Core Server-Class Processor (IBM)
  • 4.5 Silicon Debug for eDRAM or 3D TSV Stacked IC and DRAM (Duke U.)
  • 4.6 3D TSV Integration of Accelerators, FPGAs and DRAM (USC, U. of Arizona)
  • 4.7 In-Field Repair of eDRAM (Mosys)
  • 4.8 Accumulator-Based Self-Adjusting Output Data Compression for eDRAM(TE Athens)
  • 4.9 Fast Two-Bit ECC for DRAMs (Micron, Politecnico di Milano)
  • 4.10 1 Tb/s 1024 b PLL/DLL eDRAM PHY for CoWoS Application (TSMC)
  • 4.11 Non-Refresh eDRAM in High Throughput LDPC Decoder (U. of Michigan)
  • 4.12 22 nm Tri-Gate eDRAM Cache for Improved Graphics Performance (Intel)
  • 4.13 Using Spatial Locality to Reduce Refresh Energy in eDRAM Modules (U. Illinois, HPCA)
  • 4.14 A BIST for DRAMs That Reuses Refresh (ITT)
  • 4.15 Circuit and Design of Microprocessor with Trench eDRAM (IBM)

5.0 1T-DRAMs / Capacitorless DRAMs

  • 5.1 Overview of 1T (Capacitorless) DRAMs
  • 5.2 1T DRAM/NVM Using FE and CT Memory (NCTU, TNU, RCAS, TQRPO, TSMC)
  • 5.3 Bulk Planar SiGe Heterostructure ZRAM with low Vt Variability (IIT Bombay, U. Stuttgart)
  • 5.4 FinFET Based Tunnel FET Used as a Capacitorless DRAM Cell (EPFL)
  • 5.5 Disturbance for 4F2 GAA 1T-DRAM with Wide Trench Body (Nat. Sun Yat-SenU)
  • 5.6 Fast FinFET 1T DRAM with Long Retention Time
  • 5.7 1T DRAM Using Fin Tunnel-FET with Doped Pocket (Ecole Polytech Fed. de Laussanne)
  • 5.8 Using Extended Body FinFET with GIDL Write for 1T-DRAM (Nat. Sun Yat-Sen U)
  • 5.9 1T-DRAM Memories Using 3D SOI substrates (U. of Granada, IMEP and INP MINATEC)
  • 5.10 A Capacitorless DRAM with Raised Source Structure (Nat. Sun Yat-Sen U.)
  • 5.11 SOI Double Gate Pillar 1T-DRAM with Fin and bottom gate (Nat. Sun Yat-Sen U.)
  • 5.12 Vertical SOI MOSFET with Trench Body for 1T-DRAM and HPT (Nat. Sun Yat-sen U)
  • 5.13 Impact of Spike Anneal Peak Temp on 1T-DRAM Retention(U.Sao Paulo, IMEC) C.
  • 5.14 Endurance of 1T Floating Body DRAM on UTBOX SOI (IMEC, ISEN-Toulon, Micron)
  • 5.15 2T Dual Port Capacitor-less DRAM (Fudan U.)
  • 5.16 Bias for 1T-DRAM Using Biristor Mode Operation (KAIST)
  • 5.17 Thermal Characteristics of Vertical Bulk BJT 1T-DRAM (Tohoku U., JST-CREST)
  • 5.18 Fast 2T Floating-Body Cell for eDRAM (U. of Florida)
  • 5.19 GaP Source-Drain SOI 1T-DRAM Scaled to 20 nm (Stanford U., Applied Mat)
  • 5.20 Operation of a 1T Bulk Capacitor-less DRAM (Fudan U.)
  • 5.21 UTBOX SOI 1T-DRAM
  • 5.21.1 Retention Time of UTBOX SOI 1T-DRAM (U.of Sao Paulo, IMEC and KU Leuven)
  • 5.21.2 Two-Sided Read Window in SOI UTBOX 1T-DRAM (U. Sao Paulo, IMEC, KULeuven)
  • 5.22 1T-DRAM Using Vertical GAA DRAM Cell with GaP Source/Drain (Stanford U.)
  • 5.23 Improving Processing of GaP for Use in 1T-DRAM (Stanford U., Applied Materials)
  • 5.24 Vertical SOI Capacitorless 1T-DRAM cell with Trench Body (Nat. Sun Yat-Sen U.)

6.0 FeDRAMs

  • 6.1 Overview of FeDRAM Embedded Memories
  • 6.2 FeDRAM Embedded in Logic with HfO2 Ferroelectric (Yale)
  • 6.3 3D Ferroelectric Deep Trench Capacitors Based on Al:HfO2 (Fraunhofer)
  • 6.4 1T Hf-based Ferroelectric MOSFET DRAM-Like Memory (NTNU, NCTU)

7.0 Innovative eDRAM Devices

  • 7.1 Performance Analysis of 32 nm FD-SOI DRAM cell Array (Jadayput U.)
  • 7.2 Scaled Unified-RAM Using 1T-DRAM and BE-SONOS (KAIST)
  • 7.3 SOI Field Effect Diode DRAM ( George Mason U., T.I.)


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