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Non-Volatile Memories Embedded in Processing Logic: Applications, Technologies, Vendors, Foundries, June 2016
(eFG Single Poly Flash, eSplit-Gate Flash, eCharge-Trapping Flash, eNanoParticle Flash, ePCM, eMRAM, eFRAM, eCB-RAM, eRRAM)

Requirements for non-volatile memory embedded in processing logic differ significantly from those of standalone non-volatile memory. Process compatibility with CMOS logic becomes a significant factor in cost reduction for embedded NV (eNV) memory. Flash microcontrollers tend to be more application specific than conventional high performance MPU which requires that the embedded emory function must also reflect the application. For this reason a variety of eNV memory cells have been developed. Floating gate eFlash is frequently made with single poly and split gate cell architectures both of which can be made CMOS compatible with no process adders. Charge trapping (SONOS/ MONOS) Flash is commonly used for eFlash since a single poly layer can be used in a low cost CMOS compatible process and earlier reliability issues have been solved. Some emerging memories have properties that are applicable to eNV memory. These include: Nanoparticle (NP) memory, Phase Change Memory(PCM), Conductive Bridge Ram (CB-RAM), Metal Oxide Resistive RAM (ReRAM), Magnetic RAM (MRAM), Ferroelectric RAM (FRAM) and Thin Film (Polymer) RAM. The production and development status of these emerging memories for use as eNV memory in application specific processing circuits is discussed. The technology and capabilities of companies developing these circuits and cells, and the foundries that process them are discussed in the final sections if this report.

300+ pages.

Non-Volatile Memories Embedded in Processing Logic: Applications, Technologies, Vendors, Foundries, June 2016
(eFG Single Poly Flash, eSplit-Gate Flash, eCharge-Trapping Flash, eNanoParticle Flash, ePCM, eMRAM, eFRAM, eCB-RAM, eRRAM)

Table of Contents

1.0 Overview of Embedded Non-Volatile Memories

2.0 Embedded Non-Volatile Memory Market Trends Overview

  • 2.1 Flash Microcontroller Market Overview

3.0 MCU with eNVM Technology Overview

  • 3.1 Flash MCU Production Technology Overview
  • 3.2 Comparisons of the Various Non-Volatile Embedded Memories Characteristics.
    • 3.2.1 Comparison of Various Emerging Memories Used as eNV Memory
    • 3.2.2 Comparison of Write Cycle of Various Embedded Flash Memory

4.0 Applications for Flash Microcontrollers

  • 4.1 Overview of Applications for Flash Microcontrollers
  • 4.2 Automotive Applications
    • 4.2.1 Overview of the Automotive Market
    • 4.2.2 Automotive MCU with Video Graphics and eFlash (Cypress)
    • 4.2.3 eMONOS in High Temperature Automotive applications.(Renesas)
    • 4.2.4 Automotive Temperature MRAM in Motorcycles
    • 4.2.5 Automotive Entertainment
    • 4.2.6 Automotive Satellite Positioning
    • 4.2.7 Automotive Sensors
    • 4.2.8 Secure Automotive (STMicro)
    • 4.2.9 Automotive Airbag Controllers (STMicro)
  • 4.3 Big Data Search Engines and Look-up Tables
    • 4.3.1 256bit Wordlength 2.5T1R ReRAM TCAM in CMOS Logic (NTHU, TSMC, NCTU)
    • 4.3.2 Spintronics CAM Using Spin-Orbit-Torque Programming (Avalanche Tech.)
    • 4.3.3 3T1R nvTCAM Using MLC ReRAM with <1 ns Search Time (NTHU, ITRU, NCTU)
    • 4.3.4 nvLUT with ReRAM for Reconfigurable Logic (ITRI, Nat. Taipei U., NTHU, Min Shin U.)
  • 4.4 Smart Digital Utility Smart Meters
    • 4.4.1 Overview of Smart Meter Market
    • 4.4.2 Summary of Smart Meter Chips and Flash Capacity
  • 4.5 Wireless Sensor Networks / Internet of Things
    • 4.5.1 MCU for extending Battery life in Sensing Applications
    • 4.5.2 Wireless SoC with Embedded Flash for IoT (Silicon Labs)
    • 4.5.3 Plug & Play WiFi MCU with eFlash for IoT (Silicon Labs)
    • 4.5.4 Sensor Hubs (STMicroelectronics)
    • 4.5.5 Industrial High Performance IoT Markets (Atmel)
    • 4.5.6 Low Power IoT MCU with Embedded Flash (Cypress)
    • 4.5.7 Remote Controls and Thermostats
    • 4.5.8 Bluetooth Module Add-on for IoT Designs (Silicon Labs)
    • 4.5.9 Bluetooth Smart Beacons
    • 4.5.10 OxRAM Pulse Latch in nvFF for IOT Low Standby Power Circuit (U. Grenoble Alpes)
    • 4.5.11 Secure IoT
    • 4.5.12 Circuits for Solar Harvesting
    • 4.5.12.1 IoT Circuit Using ReRAM with Solar Harvesting (Chuo University)
    • 4.5.12.2 Solar Energy Harvesting Power Management IC (Cypress)
    • 4.5.12.3 Flash MCU for IoT Using Energy Harvesting (STMicro)
  • 4.6 Communications for IoT
    • 4.6.1 Near Field Communications (NFC) Tags (NXP)
    • 4.6.2 Bluetooth Family (Silicon Labs)
    • 4.6.3 Long Range Connectivity for IoT (TI)
    • 4.6.4 Bluetooth Support ICs (Toshiba)
    • 4.6.5 Single Wire Serial Self-Powered EEPROM for IoT Wearables (Atmel)
    • 4.6.6 32-bit MCU for USB Connectivity of IoT Devices (Silicon Labs)
    • 4.6.7 RFID Chips
    • 4.6.7.1 RFID Sensor Motes
    • 4.6.7.2 Dual Frequency (NFC and EPC) RFID Chip (EMMicroelectronic)
  • 4.7 Medical and Personal Network Equipment
    • 4.7.1 Market for Portable and Wearable Medical Systems
    • 4.7.2 8-bit MCU for Personal Medical Devices and wearables (Silicon Labs)
    • 4.7.3 Platform for Wearable IoT Applications (Atmel)
    • 4.7.4 CB-RAM Serial Flash Memory for Wearable Low Power IoT (Adesto)
    • 4.7.5 Security for Wearable Electronics (SM Microelectronics)
    • 4.7.6 MCU for Fitness Watch (Atmel)
    • 4.7.7 Application Processor for use in Wearable devices for IoT (Toshiba)
    • 4.7.8 LP MCU Family with Crypto engine and Dual Partition 256KB of Flash (Microchip)
    • 4.7.9 65nm Embedded Flash for wearable and healthcare equipment (Toshiba)
    • 4.7.10 NFC Tag using FRAM MCU for Wearable Applications (TI)
    • 4.7.11 40 nm eFlash in MCU Process for Low Power IoT (NXP, GlobalFoundries)
    • 4.7.12 Medical Equipment Requiring Gamma Irradiation Sterilization (Adesto)
    • 4.7.13 Low Power Flash MCU for Portable Medical Equipment (ST Micro)
  • 4.8 High Performance Mobile Systems / Smart Phones
    • 4.8.1 Smart Phones
  • 4.9 Payment Cards and Security in Home Banking
    • 4.9.1 Security in Home Banking (NXP)
    • 4.9.2 Security for Payment Applications (STMicroelectronics)
    • 4.9.3 Embedded EEPROM in Universal ID card (EMM)
    • 4.9.4 Chip Payment Cards (STMicroelectronics)
  • 4.10 Office Equipment
    • 4.10.1 USB Processors for Office Automation
    • 4.10.2 High Performance Flash Storage Systems / SSD
  • 4.11 Home Automation and Appliances
  • 4.12 Industrial Applications
    • 4.12.1 32-bit eFlash P-SoC Upgrade for 8-bit/16-bit MCU Industrial Apps (Cypress)
    • 4.12.2 Industrial Controllers With Graphics Capability
    • 4.12.3 Capacitive Touch MCU with Embedded FRAM (TI)
    • 4.12.4 Non-Volatile DAC (Microchip)
    • 4.12.5 SPI Interface Applications
    • 4.12.5.1 64 Mb P-STT-MRAM SPI Interface Samples in 55 nm CMOS (Avalanche)
  • 4.13 Motor Control
    • 4.13.1 Small System Motor Control (Silicon Labs)
    • 4.13.2 Motor Control with High Performance Analog (Toshiba)
    • 4.13.3 Control of Multiple Motors (Renesas)
    • 4.13.4 Motor Analysis System for Factory Automation (Texas Instruments)
  • 4.14 Neuromorphic Computers
    • 4.14.1 HfO2 RRAMs as Synapses for Convolutional Neural Networks (CEA-LETI)
    • 4.14.2 STT MRAM as Synapse for Neuromorphic Systems(U. Paris-Sub, CEA, Beihang U.)
    • 4.14.3 A Synapse Using Si-Based Charge-Trap Memory (Seoul Nat. U., Samsung)
    • 4.14.4 STT MRAM as a Stochastic Memristive Synapse (U. Paris-Sud, CNRS, CEA, LIST)
    • 4.14.4 Fabrication of Synapse Chips Using 3T-FeMEMs in CMOS Logic (Panasonic)
    • 4.14.5 Array-Level Learning with PCM Synaptic Devices (Stanford, U of Penn, IBM)
  • 4.15 Non-Volatile, Low Voltage and Instant-On Processors
    • 4.15.1 nvMCU with 65 nm eReRAM for NV Processing (Tsinghua U., NTHU, U. of Calif.LA)
    • 4.15.2 Single RRAM nvSRAM for Reduced Re/Store Energy (NTHU, NDL, NCHU, EOL ITRI)
    • 4.15.3 ReRAMs Optimized for FPGA and for nvFF (CEA, LETI)
    • 4.15.4 ReRAM based Non-Volatile Flip-Flops for Low Voltage SoCs (EPFL)
  • 4.16 Flash MCU Security
  • 4.17 Near Field Communications Tags

5.0 Embedded Floating Gate Flash Technology Development

  • 5.1 Overview of Embedded Floating Gate Flash Technology Development
  • 5.2 Single Poly eFlash and Floating Gate Logic-eNVM
    • 5.2.1 Single Poly EEPROM in CMOS for Medium Density Applications (U. Brescia)
    • 5.2.2 Scalable Single Poly eEEPROM with W CG in CMOS Logic Process (NTHU)
    • 5.2.3 3T EEPROM Devices in Conventional CMOS Logic (FlashSilicon)
    • 5.2.4 Simulation Model for Single Poly EEPROM cell (Nat. U. of Defense Tech. China)
    • 5.2.5. Byte-Alterable, HVCMOS Logic Compatible, 90 nm, 3T Cell EEPROM (Genusion)
    • 5.2.6 Select Gate Lateral Coupling(SGLC) Single Poly eNVM in HVCMOS (SK Hynix)
    • 5.2.7.1 Half-MOS Single Poly eEEPROM with P/E Bit Granularity (U.of Brescia, STMicro)
    • 5.2.8 5T Single Poly eFlash in Conventional CMOS Logic (U. of Minnesota)
    • 5.2.9 eFLash in Generic Logic Process
    • 5.2.9.1 Bit-by-Bit ReWritable eFlash in Generic Logic Process (U. of Minnesota)
  • 5.3 Embedded Split-Gate FG Flash Technology Development
    • 5.3.1 Overview of Split-Gate eFlash Technology
    • 5.3.2 Low Operating Voltage Embedded EEPROM (Shanghai Huahong Grace Semi)
    • 5.3.3 55 ns Split-Gate Flash Array for Automotive and for Smart Cards (SST/Microchip)
    • 5.3.4 Production SPICE Model for 55 nm SplitGate eFlash (CEA-LETI, Microchip)
    • 5.3.5 Peripheral Circuits for Split-Gate NOR eFlash(CAS, GSMC, Shanghai Huahong)
    • 5.3.6 2-bit/cell Split Gate Flash with Program Disturb Immunity (CAS, Huahong Grace)
    • 5.3.7 Program Disturb in 3rd Generation 90 nm Split-Gate SST Memory
    • 5.3.8 45 nm 1.5T Split-Gate eFlash Cell for Smart Phones (Samsung)
    • 5.3.9 Binary Code Inversion Method for Low Current eFlash Sense Amplifier (KAIST)
    • 5.3.10 Reduction of Program Induced Degradation for Advanced Split Gate Flash (SST)
  • 5.4 Other Embedded NV and eFlash Memories
    • 5.4.1 Integrating Double Poly NVM in Base Line CMOS (On Semiconductor)
    • 5.4.2 16Mb Twin-Bit-eNVM with Virtual Ground (CAS, Shanghai Huahong, GSMC)
    • 5.4.3 One-Time-Programmable (OTP) Cells for 16 nm FinFET Technology (Sidense)
    • 5.4.4 Using HV & Standard CMOS IP Circuitry for a low cost eMTP (Nat.Chung.Hsing U)
    • 5.4.5 High Voltage Process eFlash for Automotive (Rohm and Genusion)
    • 5.4.6 Embedded EEPROM in universal ID card (EMM)
    • 5.4.7 eFLOTOX Flash on Low Power 55 nm Logic DDC Process (Fujitsu)
  • 5.5 Peripherals, Reliability and Test for Production Embedded Flash Cells
    • 5.5.1 Over Erase Algorithm in FN-FN NOR eFlash for Reliability (U.S.di Ferrara)
    • 5.5.2 Calibration Based Asymmetric Voltage Biased Current Sense Amp (NTHU, TSMC)

6.0 Embedded Charge Trapping NV Memory

  • 6.1 Overview of Embedded Charge Trapping Memory
  • 6.2 Production Charge Trapping Memory Technologies
    • 6.2.1 On-Chip Recovery for Self-Aligned Nitride Logic NVM (NTHU, TSMC)
    • 6.2.2 Data Retention mechanisms of an embedded SP-MONOS NVM(Renesas, Hitachi)
    • 6.2.3 40nm SONOS eFLash IP-Foundry for MCU, IoT and Wearables (Cypress, UMC)
    • 6.2.4 Functioning 55 nm eSONOS for Smart Cards and IoT (Cypress, Shanghai Huali)
    • 6.2.5 Low Voltage, Low Cost SONOS Memory Technology (Cypress, UMC)
    • 6.2.6 28 nm eFlash with SG-MONOS Cell for Automotive (Renesas)
    • 6.2.7 40 nm eFlash Macro using Split-Gate MONOS Cell for Automotive (Renesas)
    • 6.2.8 Charge Trapping Flash Memory Devices (Spansion)
  • 6.3 Development of Embedded Charge Trap Memories
    • 6.3.1 90nm 1T-MONOS eFlash Macro for High Performance Automotive(Renesas)
    • 6.3.2 28 nm eFlash SG-MONOS for Automotive (Renesas)
    • 6.3.3 Blocking and Tunnel Oxide of DT BE-SONOS Performance (Macronix, NCTU)
    • 6.3.4 eNVM Using Trapped Electrons in CMOS High-k Gate Dielectric (IBM, UCLA)
    • 6.3.5 Charge Trap eFlash for Low Energy Applications(ST-Micro, A-Marseille U.)
    • 6.3.6 P/E Characteristics of 2T SONOS NVM Cell (SK Hynix, Sogang U.)
    • 6.3.7 MOHOS NV Memory Device using a ZrO2 Trapping Layer (Chang Gung U)
    • 6.3.8 3D Fin-FET MANOS Flash with Al2O3 Blocking Layer (AIST, NIMS)
    • 6.3.9 Trapping Properties of HfO2 CT eNVM (U. of Udine, MDM Lab IMM-CNR)
    • 6.3.10 2T SONOS NVM in HV CMOS for in MCU for Touch Screens (SK Hynix, Wingcore)
    • 6.3.11 CT NVM with IGZO Channel & ZnO CT Layer (Kyung-Hee U. E&T Res. Inst.)
    • 6.3.12. 28 nm eFlash MONOS Technology for MCU (Renesas)

7.0 Nanocrystal Embedded Floating Gate Flash Production and Technology

  • 7.1 Overview of Nanocrystal eFlash Memories
  • 7.2 Production NC Memories
    • 7.2.1 Thin Film Nanocrystal eFlash and eEEPROM Production (NXP)
  • 7.3 Research and Technology Development of NC/NP Memories
    • 7.3.1 Inorganic Spin-Coated NP Capacitive Memory (IIS Bengaluru)
    • 7.3.2 Thin Film Si NP Al2O3/TiO2 MOS Memory ( Ctr.Microsystems, Abu Dhabi)
    • 7.3.3 An Inogranic AlPO Dielectric and CdTe NP Memory (IIS, Bengaluru)
    • 7.3.4 Memory Characteristics of Graphene Nanoplatelet Memory (Masdar Inst. of ST)
    • 7.3.5 Flexible 2-Terminal RRAMs with NP embedded Polymer Layer (Nat. U. of Singapore)
    • 7.3.6 Conjugated Polymer NP as Nano FG Electrets for NV Memory (Nat. Taiwan U)
    • 7.3.7 Low Voltage WORM Memories for Anti-Fuses/Anti-Fuses (VTT Tech REs. Ctr)
    • 7.3.8 Effect of Annealing Time on Ge NP MOS Memory Behavior (UFABC)
    • 7.3.9 Memory Properties of Graphene NC in polymer Matrix (Nat. Inst. for R&D, Romania)
    • 7.3.10 Si-NPs in ZnO-based Spin-on Charge Trapping Memory (Ctr. for Microsys. AbuDhabi)
    • 7.3.11 Memory Effect with InN NP in ZnO Charge Trapping Layer (Masdar IST)
    • 7.3.12 CdSe Nanocrystals in Zr:HfO2 on P-type Silicon Wafers (Texas A&M Univ.)
    • 7.3.13 Study of Gate using ZnO Silicon Nanoparticle Charge Trapping (Masdar IST)
    • 7.3.14 Operation of Al/Au Nanoparticles in Polystyrene Layer (Hanyang U.)

8.0 Embedded Phase Change Memory - Technology, Test and Reliability

  • 8.1 Applications for Embedded Phase Change Memory
    • 8.1.1 64K Cell PCM Neuromorphic Core for IoT Systems (IBM)
    • 8.1.2 PCM-based TCAM for Big Data Computing(U. of Wisconsin)
    • 8.1.3 Two PCM Devices in a Large Artificial Neural Network of 164,885 Synapses(IBM)
    • 8.1.4 Sneak Path Encryption for PCM NV Memory (PolyNYU, RutgersU, NYU, AbuDhabi)
    • 8.1.5 2T2R TCAM Made Using Phase Change Memory (IBM)
    • 8.1.6 Using PCM for Low Power Synapses (CEA-LETI, CEA-LIST, INRIA)
  • 8.2 Production PCM Devices
    • 8.2.1 32 Mb PCM Compatible with Flash SPI (Being Adv. Memory Corp.)
    • 8.2.2 .PCM Company Ceased Operation (TechEye)
  • 8.3 Technology and Development of PCM
    • 8.3.1 Overview and Basic PC-RAM Operation
    • 8.3.2 Design Solutions for Enhancing PCM Reliability (Arizona State U., Intel)
    • 8.3.3 Interface Engineering to Reduce PCM Programming Current (HK UST, Peking U)
    • 8.3.4 Embedded ROM PCM and RAM PCM in an MCU Application (IBM, Macronix)
    • 8.3.5 Reliability of eGST PCM for High Temperature Regimes (STM, Politec. di Milano)
    • 8.3.6 Using Error Correction for Limited Endurance in PCM (U. Campinas)
    • 8.3.7 Intrinsic Retention Statistics in PCM Arrays (P. di Milano, U. Milano-Bicocca, Micron)

9.0 Embedded Conductive Bridge Resistance RAMs

  • 9.1 Overview of Conductive Bridge Resistance RAMS
  • 9.2 Applications of Embedded CB-RAM
    • 9.2.1 Second Generation CB-RAM for IoT (Adesto)
    • 9.2.2 CB-RAM Optimized for FPGA and for nvFF (CEA, LETI)
  • 9.3 Production of CB-RAM
    • 9.3.1 45 nm CBRAM to Run in TPSCo's 300 mm Fab (Adesto, TPSCo)
    • 9.3.2 10nm Cu Electrode Subtractive Dry-Etch Pattern for CB-RAM (IMEC,TokyoElectron)
    • 9.3.3 2nd Generation CB-RAM Cells with High Temperature Retention (Adesto)
    • 9.3.4 eCBRAM Technology To Run at Altis Foundry
  • 9.4 Development Studies for CB-RAM
    • 9.4.1 CB-RAM Variability Caused by Multiple CF (IMEC, KU Leuven, U.Gent)
    • 9.4.2 Better Retention of LRS in CB-RAM with Single Filament Formation (IME, CAS)
    • 9.4.3 Origen of Deep RESET and Low Variability of Pulse-Write CB-RAM (IMEC)
    • 9.3.4 CB-RAM Bit-Error Rate from Ionizing Radiation(Arizona State U, Adesto Tech)

10.0 Embedded Resistance RAM Technology

  • 10.1 Overview of eReRAM Technology
  • 10.2 Production eRRAM Technology
    • 10.2.1 Au/Si embedded ReRAM Integrated in Logic (Crossbar, SMIC)
    • 10.2.2 Analysis of 8-bit MCU with 64kB of embedded TaOx ReRAM (Jet Propulsion Lab)
  • 10.3 Embedded RRAM Development
    • 10.3.1 Sense Amp and Write Termination Method for eRRAM Macro (NTHU, TSMC)
    • 10.3.2 2T2M Memristor Cell for Stable RRAM Modules (Nile U., AinShams U., Cairo U.)
    • 10.3.3 Read Circuits for Scaled ReRAM ( NTHU, Nat Chung Hsin U, I-shou U., ITRI, NDL)
    • 10.3.4 Collaboration on eRRAM Technology Development (Rambus, Freescale)
    • 10.3.5 16Kb HfO ReRAM in 28 nm HKMG Process for FDSOI MCU (STMicro)
    • 10.3.6 Chip Level Characterization of 28 nm eRRAM (STMicro, CEA LETI, U. de Lyon)
    • 10.3.7 Characterization 1T1R 4K RRAM (U. diFerrara, IHP, TU Berlin, Brandenburg TU, IASA)
    • 10.3.8 65 nm 2Mb ReRAM with Vertical Parasitic BJT Switches (NTHU, ITRI, TSMC)
    • 10.3.9 CMOS 28 nm 1Mb ReRAM 0.27 - 1V READ (Nat. Tsing Hua U, TSMC)
  • 10.4 eRRAM Process and Fabrication
    • 10.4.1 A Low Cost Manufacturable 16 nm FINFet RRAM Logic Process (NTHU, TSMC)
    • 10.4.2 An Optimized TiN/TaOx/HfO2/TiN RRAM (Tsinghua U., Rambus)
  • 10.5 Reliability of Embedded ReRAM
    • 10.5.1 Cycling Degradation of HfOx ReRAM ( DIEB, Politec.di Milano, IU.NET, Micron)
    • 10.5.2 Data Retention Study in HfO2 RRAMs (DIEB, Politec. de Milano, IU.NET)
    • 10.5.3 ReRAM Retention Prediction Based on 3D Filament Structure (Panasonic, Kyoto U.)
    • 10.5.4 RRAM Defect Modeling and Failure Analysis Test (National Tsing Hua U.)
    • 10.5.5 MO-ReRAM with Control of Capacitive Surge Current During Write (Rambus)
    • 10.5.6 Effect of Single Event Upsets on MCU with eReRAM ( NASA Goddard SFC)
    • 10.5.7 Write Disturb Analysis of Cross-Point RRAM (PekingU, StanfordU, Arizona St.U)

11.0 MRAM Memory Embedded in Logic

  • 11.1 Overview and Introduction to Embedded MRAM technology.
    • 11.1.1 Overview
    • 11.1.2 Introduction
  • 11.2 Embedded STT-MRAM Market and Applications
    • 11.2.1 STT-MRAM Market Estimates
    • 11.2.2 Serial Access Domain Wall MRAM for DSP Design (Korea U., U. of S. Florida)
    • 11.2.3 Reducing Power in Instant ON/OFF SoC by Basic Memory Design (Spintec)
    • 11.2.4 Evaluation Flow for Memory Hierarchy of eMemory ( U. of Montpellier)
    • 11.2.5 System Level Study of STT-MRAM in L1 Data Cache (U. Computer de Madrid)
    • 11.2.6 STT-MRAM for L2/L3 Cache in Low Power Systems (Tohoku U.)
    • 11.2.7 eSTT-MRAM Energy and Cost Trade-offs for Mobile Systems (Qualcomm)
    • 11.2.8 PMA STT-MRAM for Embedded Cache Memory in HP CPU (Toshiba)
    • 11.2.9 Variable NV Memory Arrays for Adaptive Computing (Toshiba)
  • 11.3 Embedded STT-MRAM Production
    • 11.3.1 Everspin Samples Single Foundry 256Mb MRAMs (Everspin, GlobalFoundries)
    • 11.3.2 Perpendicular STT-MRAM Production (Avalanche)
    • 11.3.3 64-Mb STT-MRAM Production (Everspin)
    • 11.3.4 Crocus eMRAM Production Technology
    • 11.3.5 Sub-5 ns Write with PMA STT-MRAM Chips (TDK Headway)
  • 11.4 eMRAM Research and Development Studies
    • 11.4.1 Spin Orbit Torque Embedded Memory for nvCAM
    • 11.4.2 STT-MRAM Cell Trading Off Area and Source Line Resistance (KU Leuven)
    • 11.4.3 OTP Anti-fuse STT-MRAM Cell Integrated in Mb STT-MRAM (TDK-Headway)
    • 11.4.4 Analysis of SOT-MRAM for On-Chip Cache Hierarchy (Karlsruhe Inst. of Tech.)
    • 11.4.5 Reducing Latency in STT-MRAM Using Field Assisted Writing (U. of Rochester)
    • 11.4.6 Domain Wall Coupling STT MRAM for On-Chip Cache (Purdue)
    • 11.4.7 1Mb eSTT-MRAM in 65 nm node with 3.3 ns access time (Toshiba)
    • 11.4.6 Sub 20 nm p-MTJ Stack for Standalone and Fast Embedded Memory (IMEC)
    • 11.4.7 Reduced Power and Improved Margins Using Asymmetric FET (Purdue, Penn
    • 11.4.8 8Mb Perpendicularly Magnetized MTJ STT-MRAM Test Chip (TDK-Headway)
    • 11.4.9 Overview of Current MRAM Scaled Technologies (AIST, Osaka U., CREST, Toshiba)
  • 11.5 Process and Fabrication of Embedded MRAM Technology
    • 11.5.1 Embedded STT-MRAM for Energy Efficient Mobile Systems, (Qualcomm)
  • 11.6 Test , Yield, and Reliability of eMRAM
    • 11.6.1 Unified Design Framework to Enhance Yield of STT-MRAM (Purdue Univ.)
    • 11.6.2 Robustness Margin for Read/Write of STT-MRAM Cell (Polit. di Torino)
    • 11.6.3 Soft Error Tolerant MRAM Latches (Sharif Univ. of Tech.)
    • 11.6.4 OS-MLS codes for Multi-Bit Error Correction in STT-MRAM (Beihang Univ.)

12.0 Embedded FeRAM

  • 12.1 Overview of Embedded FeRAM
  • 12.2 Embedded FeRAM Applications
    • 12.2.1 Wearable Noise Tolerant ECG Processor Monitoring System (Kobe University)
    • 12.2.2 Wireless Computing/Energy Harvesting Sensor Node (TU Darmstadt, Farunhofer)
    • 12.2.3 Lo Power 6T-4C NV SRAM using Charge Sharing & Non-Precharge ( Kobe U., Rohm)
    • 12.2.4 FeRAM MCU Energy Harvesting Shut-Down Only on Power Loss (U.Southhampton)
    • 12.2.5 14 uA ECG Processor with FeRAM for Heart Rate Logging (Kobe U)
    • 12.2.6 Wearable ECG System using 64kB eFeRAM Data Buffer (KobeU, Rohm, Omron)
    • 12.2.7 NFC Enabled Wearable Bio-Patch Using Processor with Embedded FeRAM (TI)
    • 12.2.8Artificial Synapses Using 3T-FeMEM for Multishaded Image Recognition (Panasonic )
    • 12.2.9 Artificial Synapses using 3T-FeMEM on single crystal oxide substrate (Panasonic)
    • 12.2.10 Smart RFID Tag Using FeRAM MCU, EEPROM (U. of Salento)
    • 12.2.11 4.4 32b MCU SoC Using NV Logic with 100% Digital State Retention (TI)
  • 12.3 Embedded FeRAM Production
    • 12.3.1 Companies with Production FeRAM
    • 12.3.2 Test and Reliability of Production FeRAMs
    • 12.3.3 .Effect of Heavy Ion Radiation on a 4Mb FeRAM (U. de Montpellier)
    • 12.3.4 Single Event Testing of Commercial FeRAMs (Test Res. Inst. Guangzhou)
    • 12.3.5 Radiation Effect of Sterlization on FeRAM (Osaka U.)
  • 12.4 Embedded nTmC FeRAM Development
    • 12.4.1 Eliminating Self-Crosstalk in Multibit FeRAM memories (KAIST)
    • 12.4.2 Triple Protection Structure for Low Voltage COB FRAM (Fujitsu)
    • 12.4.3 2T2C FeRAM with TFT& P(VDF-TrFE) Copolymer (Micron, U. of Texas Dallas)
    • 12.4.4 P(VDF-TrFE) Copolymer Organic FeFET and FRAM Characterization(Slovak U.)
    • 12.4.5 Control of Hot Atom Damage in Ferroelectric Devices (Purdue U., TI)
    • 12.4.6 Printed TFT Decoder for Fe-Mem (IM2NP UMR CNRS, Aix Marseille U., CEA-LITEN)
    • 12.4.7 Flexible FeRAM Using Ultrathin Monocrystalline Silicon (KAUST)
    • 12.4.8 Mechanical Stress Effects on PZT capacitors embedded in CMOS (TI)
    • 12.4.9 BL Segmented Array FRAM for High Speed & Low Power (UEST, UCF, CAS, Huawei)
    • 12.4.10 Radiation Tolerance of Commerical FeRAMS (U. of Electronics S&T China)
    • 12.4.11 Sense Amplifier Compensation for Random and Systematic Offset (TI)
    • 12.4.12 Ferroelectric Deep Trench Capacitors for Use in 1T1C FRAM (Fraunhofer Inst.)
    • 12.4.13 NAND-Like Organic FeMEM Array on Flexible Substrate (KU Leuven, LAE/OME, IMEC, Amity U., Politecnico di Torino, TNO-Holst)
    • 12.4.14 HfO2 Ferroelectric (Fraunhofer,NaMLab,TU-DRESDEN,Globalfoundries,Bosch Solar,ORNL)

13.0 Embedded 1T Ferroelectric Memories (FeMOS, FeFET, FeDRAM)

  • 13.1 Overview of 1T FeMOS Memories
  • 13.2 Applications for 1T FeMOS Memories
    • 13.2.1 Low Power Fe-MTFT LCD with a low refresh rate (Kyung Hee U, E&T Res. Inst.)
    • 13.2.2 NV Boolean Logic Based on a FeTunnel Memristor(UParis-Sud, CNRS, BeihangU)
    • 13.2.3 Impact Energy Harvester with FeFET Memory (Panasonic)
    • 13.2.4 A 3.4 pJ FeRAM NV D flip-flop in Digital Systems(TI, MIT, Cypress)
  • 13.3 Production of embedded FeRAM
    • 13.3.1 Wafer-Level FeRAM Sales (Cypress)
  • 13.4 Development for 1T FeFET Memories
    • 13.4.1 Circuit Models for Ferroelectric-Logic Circuits (Cornell U.)
    • 13.4.3 Single Domain Switching HfO FeFETs Enabling MLC FeFET (NaMLab, Fraunhofer, TU Dresden, GlobalFoundries, Politecnico di Milano).
    • 13.4.4 Quasi Single-Grain PZT on Polysilicon TFT NV Memory (Seoul Nat. U.)
    • 13.4.5 Back-Gate FeFET using PZT (Tsinghua U, U. ES&T, NCNT)
    • 13.4.6 HfZrO FeFET with Fast Switching and Near Ideal SS (NCTU, NTNU, NTHU)
    • 13.4.7 High Endurance, Slow Polarization Relaxation NP-FeFET Memory (NCTU, NTNU)
    • 13.4.8 Antiferro & Ferroelectric HZO Coupled for Low Power Circuits (NTNU, NTU, ITRI)
    • 13.4.9 Scaling Effect on HfO2 FeFET Performance (NaMLab,Fraunhofer CNT, Global Foundries)
    • 13.4.10 Simulation of FeFET-based Logic Circuits and Sense Amplifier(Xiangtan U)
    • 13.4.11 Properties of Single Layer Graphene PZT FeFETs (Tsinghua Nat. Lab for IST)
    • 13.4.12 Carbon Nanotube TFT Transistors with BNdTiO Gate (Yunnan Normal U, Xiangtan
    • 13.4.13 HfO2 FeRAM Endurance Limitation (NaMLab, TU Dresden, Fraunhofer, GlobalFoundries)
    • 13.4.14 Capacitor-less DRAM Using FE-DRAM FET (Yale Univ.)
    • 13.4.15 FeDRAM Memory Using Ferroelectric ZrHfO2 in a pMOS FET (NTNU, NCTU)
    • 13.4.16 Potential of Ferroelectric Si:HfO2 (NaMLab, FraunhoferCNT, Globalfoundries, TU dresden)

14.0 Thin Film Memories

  • 14.1 Thin Film Ferroelectric Memories
    • 14.1.1 Memory & Logic TFTs for a Display Driving Circuit (Kyung Hee U., E&T Res Inst.)
    • 14.1.2 Ultrathin Ferroelectric Polymer Film Memories (KAIST)
    • 14.1.3 Printed Rewritable Ferroelectric Thin Film Memory (ThinFilm Tech.)
    • 14.1.4 Flexible Memory Devices with a-InGaZnO TFT (Inst. of Tech., Zurich)
  • 14.2 Thin Film Charge Trapping Memories
    • 14.2.1 Photostable Transparent TFT NVM with IGZO Channel & ZnO CT (Kyung Hee U.)
    • 14.2.2 Transparent Flexible NVM TFT Using IGZO Channel and ZnO CT (Kyung Hee U)
    • 14.2.3 a-IGZO TFT NVM with Defect Enginr'd Alumina Dielectric (Sun Yat-sen, GuangdongU)
    • 14.2.4 Thin Film ZnO CT IGZO Channel Top Gate NVM(Kyung-Hee, ETRI, KAIST)
    • 14.2.5 Fast Organic Charge Trapping Polyimide Memory FETs (NCKU, Daxin Mat. Corp
    • 14.2.6 Charge Trap NVM with IGZO Channel & ZnO CT Layer (Kyung-Hee U.E&T Res. Inst.)
  • 14.3 Polymer Memory with Quantum Dot Trapping Layer
    • 14.3.1 Polymer NVM with Embedded Graphene Quantum Dots (Fuzhou U., Hanyang U.)

15.0 Companies Supplying or Developing Products with Embedded Non-Volatile Memory

  • 15.1 Adesto Technologies
  • 15.2 Atmel (A subsidiary of Microchip)
  • 15.3 Avalanche Technology
  • 15.4 Contour
  • 15.5 Crocus Technology
  • 15.6 Cypress (acquired Spansion and Ramtron)
  • 15.7 EM Microelectronics
  • 15.8 Energy Micro (now Silicon Labs)
  • 15.9 Everspin
  • 15.10 FlashSilicon
  • 15.11 Freescale (Now NXP)
  • 15.12 Fujitsu
  • 15.13 Genusion
  • 15.14 Huawei Technology
  • 15.15 SK Hynix
  • 15.16 IBM
  • 15.17 Intel
  • 15.18 Microchip (bought Silicon Storage Technology, buying Atmel)
  • 15.19 Micron
  • 15.20 NXP (acquired Freescale in 2016)
  • 15.21 On Semiconductor
  • 15.22 Panasonic
  • 15.23 Qualcomm
  • 15.24 Renesas
  • 15.25 Rohm
  • 15.26 Samsung Semiconductor
  • 15.27 Silicon Labs (bought EM Micro)
  • 15.28 Spansion (now part of Cypress)
  • 15.29 Spintec
  • 15.30 STMicroelectronics
  • 15.31 TDK Headway
  • 15.32 Texas Instruments
  • 15.33 Thin Film Electronics
  • 15.34 Toshiba
  • 15.35 WingCore
  • 15.36 Xinnova

16 Embedded Non-Volatile Memory Foundries

  • 16.1 Altis Semiconductor
  • 16.2 Austria Microsystems/(AMS) Foundry (Austria)
  • 16.3 Crocus Nanoelectronics (Crocus/Rusnano)
  • 16.4 Dongbu HiTek
  • 16.5 Global Foundries
  • 16.6 Huahong Grace Semiconductor Manufacturing Corporation(China)
  • 16.7 HuaHong NEC (see Huahong Grace Semiconductor)
  • 16.8 Macronix
  • 16.9 MagnaChip
  • 16.10 Mie Fujitsu (MIF)
  • 16.11 Shanghai HuaLi Micro
  • 16.12 Silterra Malasia (www.silterra.com
  • 16.13 SMIC (China)
  • 16.14 TowerJazz Semiconductor Panasonic (TPSCo)
  • 16.15 TSMC (Taiwan)
  • 16.16 UMC (Taiwan)
  • 16.17 X-Fab
  • 16.18 XMC

17. Some Companies Supplying eFlash or eNVM IP to Foundries

  • 17.1 Axon Technology
  • 17.2 eMemory
  • 17.3 Genusion
  • 17.4 Kilopass
  • 17.5 Scaleo
  • 17.6 Sidense
  • 17.7 Silicon Storage Technology

Bibliography

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