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Embedded Polymer and Flexible Memories, September 2017

Processors with embedded memories intended for use in RFID-type circuits and in wearable devices must be very low power. RFID-type circuits need to also be very low cost. The cost of these circuits can be reduced if they can be made by inkjet printing or screen printing or other techniques involving polymer circuits. Embedded memories which can be made by printing techniques or made of polymer material include: ferroelectric, charge trapping and resistive RAM memories. This technology is important for low cost circuits without requirements for high performance. For other low power IoT applications, such as the wearable recreational and medical systems, the performance of polymer circuits is not sufficient. In addition, for wearable devices, the circuits must be flexible. For these applications the performance of silicon chips is required. Technologies are also being developed for integrating systems of silicon chips on flexible substrates. These technologies are covered in this report. 65+ pages.

Embedded Polymer and Flexible Memories, September 2017

Table of Contents

1.0 Overview

2.0 Organic Ferroelectric Memories

  • 2.1 Characteristics and Features of Organic Ferroelectric Memories
  • 2.2 Printable Ferroelectric Embedded Memories
  • 2.3 IoT Applications for Thin Film Ferroelectric Memory

3.0 Polymer Ferroelectric Tunnel Junctions

4.0 Types and Characteristics of Polymer Resistive RAMs with Flexible Substrate

  • 4.1 Overview of Polymer Resistive RAMs with Flexible Substrate
  • 4.2 Parylene-C Based Resistive RAM
  • 4.3 Cu Atom Switches
  • 4.4 Inorganic Thin Film Resistive RAMs on Flexible Substrates
  • 4.5 IZO and IGZO Resistive RAM Memories
  • 4.6 Other Polymer Resistive RAMs with Flexible Substrates

5.0 Charge Trapping Nanoparticle (NP) Memory with Flexible Substrates

  • 5.1 Overview of Charge Trapping NP Memory with Flexible Substrates
  • 5.2 Carbon Charge Trapping Memory with Flexible Substrate
  • 5.3 Ink Jet Printed NP Memory
  • 5.4 Other Charge Trapping NP Memories with Flexible Substrates

6.0 Transfer of Conventional Memory Chips onto Flexible Substrates

  • 6.1 Transfer of Silicon Chips Using SOI Base Wafers
  • 6.2 Creating Thin Chips Using an Underlying Cavity
  • 6.3 Fan Out Wafer Level Packaging for Assembling Silicon Chips on Flexible Substrate


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