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Advanced Magnetic RAM (MRAM) Applications and Technologies, July 2015

The first part of this report covers current applications and applications being actively investigated for the various MRAM technologies and circuit configurations. MRAM is fast access, low leakage and CMOS-compatible which makes it potential to replace the eSRAM and eDRAM that are currently used in various levels of cache. MRAM is discussed for L1 cache through to last level cache (LLC) in multiprocessors, low power systems, and mobile systems. MRAM characteristics and configurations are also discussed for TCAM applications as well as big memory applications such as RAID storage systems and SSD. MRAM works at extended temperatures making it possible for under the hood applications in automotive and for space applications where its radiation hardness is useful. Industrial applications also use extended temperature and non-volatility. Biometric systems and neural net configurations can potentially use MRAMs. Smart cards are already built with MRAM. MRAMs can also be used in cyber-security applications where their stochastic nature lends itself to creation of physical uncloneable functions. MTJs are also used to add non-volatility to flip-flops, registers and other logic for instant-on logic functions.

Technologies discussed include STT-MRAM technology, device, design and circuit techniques. Issues with the STT-MRAM are explored including: read disturb, write power, current asymmetry, source degeneration and thermal stability. Domain wall STT-MRAM is discussed along with racetrack type domain wall technology for high density circuits. MRAMs using perpendicular magnetic anisotropy (PMA) are discussed for both standalone and embedded applications. Various process issues along with the potential of significant power reduction in embedded MRAM using PMA are covered. A standalone 8 Mb P-MTJ MRAM prototype is considered with fast access and low power. The potential for high density MRAM is covered. Issues discussed for PMA MRAM include: thermal stability and scaling.

Other topics include: voltage controlled MRAM, simulation and modeling of MRAM, and test, yield and reliability issues, spin orbit torque (SOT) devices, vertical 2D MRAMS, field assisted switching, and materials and device issues.

280+ pages.

Advanced Magnetic RAM (MRAM) Applications and Technologies, July 2015

Table of Contents

Part I : Current and Projected Magnetic RAM Applications

1.0 Overview of Possible MRAM Properties for Applications

  • 1.1 Memory Hierarchy
  • 1.2 Comparison of Parameters of Various NV Memory Technologies
  • 1.2.1 Comparison of Parameters over time in Various NV Memory Technologies
  • 1.2.2 Comparison of Parameters of Various MRAM Technologies
  • 1.3 Overview of Hybrid MRAM/CMOS Logic Circuits
  • 1.4 Comparison of Various NVM Technologies
  • 1.5 Overview of Applications for Embedded Non-Volatile Memories in MCUs (Renesas)
  • 1.6 Near Future Applications for Embedded p-STT-MRAM (Toshiba)
  • 1.7 Energy Comparison of SRAM & TAS-MRAM in L2-Cache (LIRMM-UMR CNRS, Crocus)
  • 1.8 Potential for STT-MRAM Success in Mobile Computing Systems (Qualcomm)

2.0 MRAM Replacements for Embedded SRAM Cache in MPU

  • 2.1 Overview of MRAM in Cache Memory
  • 2.2 STT-MRAM for L2/L3 Cache in Low Power Systems (Tohoku U.)
  • 2.3 System Level Study of STT-MRAM in L1 Data Cache (U. Computer de Madrid)
  • 2.4 Using PMA STT-MRAM for Cache Design (Beihang Univ.)
  • 2.5 Racetrack STT MRAM Memory for Cache Applications (Broadcom)
  • 2.6 Advantages of MRAM Embedded as Cache in Multiprocessors (U. of Montpellier)
  • 2.7 Reducing Total Power of an LLC using PMA STT-MRAM (Toshiba)
  • 2.8 Field Driven STT-MRAM to Reduce Latency & Energy in L1 Cache (U. of Rochester)
  • 2.9 Fast 1Mb 6T2MTJ Cell STT-RAM with Background Write (Tohoku U., NEC)
  • 2.10 1Mb PMA STT-MRAM Cache Memory With Low Active Power (Toshiba)
  • 2.11 A 1 Mb STT-MRAM For NV SRAM with 1.5ns Wake-up (Tohoku U.)
  • 2.12 An STT-MRAM Circuit for L2 SRAM cache (Toshiba)
  • 2.13 Fast 1T1MTJ Cache Using Asymmetric Write Characteristics of Cell (Purdue U.)
  • 2.14 Technique to Reduce Write Energy in an STT-RAM Cache (Kobe U.)
  • 2.15 Memory for Large L3 Cache (U. of Maryland)
  • 2.16 Low Power MRAM to Replace SRAM (Qualcomm, IMEC)

3.0 TCAM Applications

  • 3.1 Two NV CAM Cells Configured with MTJ and CMOS Transistors (Northeastern U.)

4.0 Big Memory Applications for MRAM

  • 4.1 State Restricted MLC STT-MRAM in Big Memory Applications (U. of Pittsburgh)
  • 4.2 RAID Storage Systems (Everspin)
  • 4.3 MRAM Cache in SSD (Everspin)
  • 4.4 MRAM to Replace DRAM as Main Memory (Penn State Univ.)

5.0 Adaptive Processing

  • 5.1 Variable NV Memory Arrays for Adaptive Computing (Toshiba)
  • 5.2 An Asymmetric Differential STT-RAM Cell Structure (U. of Pittsburgh)

6.0 Automotive Applications

  • 6.1 Automotive Temperature MRAM in Motorcycles
  • 6.1.1 MRAM using in Motorbike Engine Control Unit (Everspin)
  • 6.1.2 Engine Control Units at Extended Temperature (Everspin)

7.0 Medical Applications

  • 7.1 Healthcare Systems
  • 7.1.1 "Store Mostly" Health Care Systems (Kobe U., LEAP)
  • 7.2 Biometric Systems
  • 7.2.1 Energy Efficient STT-MRAM Sparce Data Face Recognition System (Nanyang TU)

8.0 Industrial Applications

  • 8.1 VME Board Critical Data Storage (Everspin)
  • 8.2 1Mb MRAM with Quad SPI Interface (Everspin)

9.0. Mobile Processor MRAM Applications

  • 9.1 Data Allocation Hybrid Scratch Pad Memory for Mobile Computing
    (Pace U, U Kentucky, Beihang U, TSU, Florida Intl U., Auburn U., Huazhong U.)
  • 9.2 Fast, Low Current STS in a p-MTJ for Cache in Mobile Processors (Toshiba)
  • 9.3 Using Hybrid Memory for Resource Allocation in Mobile Cloud Systems (Pace U.)
  • 9.4 Fast Mobile Processor with Nonvolatile/Volatile Hybrid Cache Memory(Toshiba)
  • 9.5 A DRAM/MRAM hybrid memory design for Fast Mobile CPU (Toshiba)

10.0 Space and Military Applications

  • 10.1 Space Applications for Radiation Induced Soft Error Immunity (Everspin)
  • 10.2 Radiation Hardened FPGAs using MTJ Spintronic Devices ( Spintec, UJF)

11.0 Smart Cards

  • 11.1 Smart Card Chips with MLU and MRAM (Crocus, ARM)
  • 11.2 MCU with Embedded NV MRAM Memory and MTJ Logic (Crocus)

12.0 Spin-Torque Sensors in Embedded Cache Memory

  • 12.1 Spin-Torque Sensors in MRAM Cache Memory (Purdue U.)
  • 12.2 Spin-Torque Sensing for Energy Reduction in on-chip Cache (Purdue U,)
  • 12.3 3-Terminal MTJ MCU for Low Standby Power Sensor Applications(NEC, TohokuU)

13.0 MRAMs in Neural Applications

  • 13.1 Overview of MRAMs in Neural Net Applications
  • 13.2 STT MRAM as a Synapse for Neuromorphic Systems (U. Paris-Sub, CEA, Beihang U.)
  • 13.3 Using STT MRAM as a Stochastic Memristive Synapse (U. Paris-Sud, CNRS, CEA, LIST)
  • 13.4 Monte-Carlo Simulations of STT-MRAM Neuro-Chips (U. of Paris-Sud)

14.0 MRAMs in Cyber - Security Applications

  • 14.1 Optimizing Emerging NVM as PUFs With MRAM Example (NanyangTU, PurdueU)
  • 14.2 A Geometry-Based Magnetic PUF Integrated in CMOS (U. of South Florida)
  • 14.3 STT-MRAM-based PUF with Multiple Response Bits per Cell (Nanyang Tech. U.)
  • 14.4 New Design of STT-MRAM-based PUFs (Politec. di Torino)
  • 14.5 Extracting PUFs from STS Characteristics in MTJ (Toshiba)
  • 14.6 Geometry-based MRAM Physically Unclonable Function - PUF (U. of South Florida)
  • 14.7 An STT-MRAM Based Physical Unclonable Function (PUF) (Nanyang TU, Purdue U).
  • 14.8 A Random Number Generator Using STT MRAM (Purdue U.)

15.0 Integration of MRAM and Logic

  • 15.1 Low Power Processor Based on "Normally-Off" Architecture Circuits (Toshiba)
  • 15.2 Various MRAM Devices for Future Integrated Spintronics CMOS (UCLA)
  • 15.3 Motion Vector Prediction Circuit Using 90 nm MTJ/MOS Circuitry (Tohoku U., NEC)
  • 15.4 Non-Volatile Logic and MRAM Model Using p-STT-MRAMs
  • 15.5 STT-Logic Configuration of 2-input XOR Using MTJ (U. of S. Florida, Everspin)
  • 15.6 MRAM Logic-in-Memory architecture (TU Wien)
  • 15.7 Cell-Base Design Flow for MTJ/MOS Hybrid Logic Circuits (Tohoku U., NEC)

16.0 MTJ Logic Circuits (Shift Resister, CAM, Latch, FlipFlop, Reconfigurable Logic)

  • 16.1 MRAM backed SRAM Cell for NV Dynamically Reconfigureable FPGA (U. of Toronto)
  • 16.2 Fast, Low Energy, Masking Error Immune PentaMTJ-Based TCAM (Aligarh Muslim U)
  • 16.3 Drawbacks of MTJ-based Resistive Computation (Univ. of Calif., San Diego)
  • 16.4 A Complementary Polarizer STT On-Chip Cache (Purdue Univ.)
  • 16.5 Local STT-MRAM Array for Zero Sleep Power Systems (Singapore UTD, Reuters, York U.)
  • 16.6 STT-MRAM Low Power Synchronous NV Logic (Singapore U. of Tech & Design)
  • 16.7 NV Flip-Flop Based on Spin Orbit Torque Coupling (SPINTEC, CEA)
  • 16.8 NV MTJ Flip-Flop Using Two-Phase Write (NUS)
  • 16.9 Power-Gated MPU Using STT MTJ NVFF with 3us Entry/Exit Delay (Tohoku U., NEC)
  • 16.10 Simulation Study of a Non-Volatile Magnetic Flip-Flop (TU Wien)
  • 16.11 Reliability Simulation of MTJ-based Logic Gates Integrated in CMOS (TU Wien)
  • 16.12 Magnetic Full Adder Circuit Based on PMA STT-MRAM (IEF, U. Paris-Sud)
  • 16.13 Magnetic Flip-Flop with Perpendicular MTJ MRAM (IEF, U. Paris-Sud, CNRS)
  • 16.14 Very Low Power MTJ Flip-Flop using Checkpointing & Power Gating (U. Paris-Sud)
  • 16.15.2 40 nm MTJ Flip-Flop using Perpendicular MTJ MRAM (IEF, U. Paris,Sud, CNRS)
  • 16.16 Synchronous Full-Adder Using Complementary STT-MRAM Cells (IEF, U. of Paris-Sud,
    UMR, CNRS, Aix-Marseille U., IM2NP-UMR CNRS)
  • 16.17 MTJ-based Logic-in-Memory (LIM) Architecture (Tohoku U.)

17.0 Novel Intrinsic MTJ Logic Circuits

  • 17.1 STT-MTJ in Intrinsic Logic-in-Memory
  • 17.1.1 MRAM-Based High Performance Stateful Logic (TU Wein)
  • 17.1.2 Reliability and Comparison of Implication and Reprogram MTJ Logic Gates (TU Wien)
  • 17.1.3 Using STT-MTJ for Intrinsic Logic-in-Memory (TU Wien)
  • 17.2 Complementary Magnetic Tunnel Junction Logic (CMAT)
  • 17.2.1 New Complementary MTJ Logic Family (Northwestern U.)

18.0 GPU With Integrated STT-MRAM

  • 18.1 GPU with Integrated STT-MRAM and Hybrid SRAM/STT-MRAM (U. of Florida)

19.0 Integrated MTJ Sensors

  • 19.1 Integration of ASIC Controller & Spintronic Sensor Array (Intl. Iberian Nanotech Inst.)
  • 19.2 Magnetic Interlayer Transmission Through PMA MTJ for 3D Integration (NTHU, ITRI)

20 MRAM Announced and Planned Production Lines

21.0 Demonstrations of Operational STT MRAM Chips

  • 21.1 64 Mb P-STT-MRAM SPI Interface Samples in 55 nm CMOS Process (Avalanche)
  • 21.2 8Mb STT-MRAM with Current-Mode Sense Amp (Samsung, SungkynkwanU).
  • 21.3 1Mb eSTT-MRAM in 65 nm node with 3.3 ns access time (Toshiba)
  • 21.4 8Mb Perpendicular STT-MRAM Prototype with sub-5ns Write (TDK-Headway)
  • 21.5 8Mb 65 nm STT-MRAM with 0.38V Operation (Kobe U., Stanford U., LEAP)
  • 21.6 Device Considerations of 90 nm CMOS 64Mb DDR3 ST-MRAM (Everspin)
  • 21.7 1.6 GT/s 64Mb DDR3 ST-MRAM Operating Characteristics (Everspin)
  • 21.8 8MB STT-MRAM Operational Test Chip (TDK-Headway Technologies, IBM)

Part II. Modern MRAM Technologies

1.0 Background on Field Programmable MTJ MRAM Technologies

  • 1.1 An overview of Current MRAM Scaled Technologies (AIST, Osaka U., CREST, Toshiba)
  • 1.2 An Overview of : STT-MRAM, DW Motion MRAM and SOT MRAM (Tohoku U.)

2.0 Spin Transfer Torque (STT) MRAM Device and Design

  • 2.1 Introduction to Spin Transfer Torque (STT) MRAM technology
  • 2.2 Reconfigurable MRAM Hybrid Codesign in Scaled Technology(Beihang U, U of Paris-Sud)
  • 2.3 4F2 STT MRAM Cell with Vertical GAA Select Device (Indian Inst. of Tech Rookkee)
  • 2.4 Embedded STT-MRAM for Energy Efficient Mobile Systems, (Qualcomm)
  • 2.5 Scaling Challenges for Sub-20 nm STT-MRAM Memory (IMEC)
  • 2.6 Spin-Based Silicon Technology Model and Cell Proposal (TU Wien)
  • 2.7 Comparison of Four MTJ Stacks for Device & Circuit Characteristics (Vellore IT U)
  • 2.8 Methods for Improved Density & Speed of MLC STT-RAM Cache(U. of Pittsburgh)
  • 2.9 Designing STT-MRAM for Embedded Memory in a CMOS Process (Georgia Tech)
  • 2.10 A 90 nm 1Mb STT-MRAM for L2/L3 Cache Memory (Tohoku U.)
  • 2.11 Simulation of Information Storage Mechanism in STT-MRAM (Huazhong U. of S&T)
  • 2.12 Minimizing Reference Resistance Distribution in STT-MRAM(A*STAR, NUS)

3.0 STT MRAM Circuit Techniques

  • 3.1 1T2MTJ STT-MRAM Cell Array with Reference Voltage Generator (Tohoku U)
  • 3.2 Dynamic Reference Sensing Method for Scaled STT-MRAM (Beihang U., U. Paris-Sud)
  • 3.3 Current-Mode Sense Amp for 8Mb STT-MRAM (Samsung, SungkynkwanU).
  • 3.4 65 nm STT-MRAM with 0.38V Operation (Kobe U., Stanford U., LEAP)
  • 3.5 Reference Study and New Reference Method for STT-MRAM (Yonsei U, Qualcomm)
  • 3.6 Self Terminated Write Driver with Data Write Completion Monitoring (Tohoku U.)
  • 3.7 Variation Tolerant Sensing for Advanced Node STT MRAM (BehangU, U. Paris- Sud
  • 3.8 Dynamic Reference to Improve MRAM Sensing Reliability (Beihang U.)
  • 3.9 STT-MRAM Sensing Circuit with Self-Body Biasing (Yonsei Univ., Qualcomm)
  • 3.10 Offset Canceling Triple State Sense Circuit for STT-MRAM (Yonsei U., Qualcomm)
  • 3.11 Four Terminal MRAM Delay Control Circuit (NEC, Tohoku U.)
  • 3.12 Circuit for Minimizing Reference Resistance in an STT-MRAM (A*STAR, NUS)
  • 3.13 Read Stability and Write Ability of Fast Access STT-MRAM (Tohoku University)
  • 3.14 Novel Circuits for Building a 16 kb STT-MRAM (Xi'dian U., U. of Paris-Sud, Beihang U)
  • 3.15 Split Path Sensing Circuit for STT MRAM (Yonsei U., Qualcomm)
  • 3.16 Offset-Canceling Triple State Sensing Circuit for STT-RAM (Yonsei U, Qualcomm)
  • 3.17 Reference Calibration Technique for Body-Voltage Sense Circuit (U. of Calif. LA)
  • 3.18 Differential STT-RAM Cell Structure with Two Modes (U. of Pittsburgh).
  • 3.19 STT-MRAM bit cell with ROM Overlay (Purdue University)
  • 3.20 STT-MRAM Sensing Circuit with Self Body Biasing (Yonsei U., Qualcomm)
  • 3.21 Improved Endurance using Balanced Write Path for 40nm 1Mb STT-MRAM (TSMC)

4.0 STT MRAM Device, Process and Process Techniques

  • 4.1 P-MTJ Stack Compatible with 420 C Anneal CMOS BEOL Process (Tohoku U.)
  • 4.2 Oxygen Showering for Damage Suppression of sub-20 nm p-MTJ(TohokuU, Samsung)
  • 4.3 Self Aligned 2 Step RIE Process for Patterning MTJ on 300 mm Wafers (Applied Mat.)
  • 4.4 1T1MTJ STT-MRAMWith FinFET Access Transistors (U. of Southern Calif.)
  • 4.5 Process Method for Scalable STT-MRAM With Reduced Process Damage (LEAP)
  • 4.6 New Reaction Etching for Magnetic Material for MRAMs (Tokyo Electron, Tohoku U.)
  • 4.7 FinFET based STT-MRAM Bit-Cell (Birla IT)
  • 4.8 Low Temperature Stability of MTJ Patterned by RIE (U. of Calif. San Diego)
  • 4.9 Improved Switching Margin with 20 nm iPMA MTJ Structure (Samsung)

5.0 Issues with STT MRAM

  • 5.1 Read Disturb and Readability in an STT MRAM
  • 5.1.1 Pulsed Read for 1T1R STT-MRAM to Reduce Read Disturb (Georgia Inst. of Tech.)
  • 5.1.2 3-Terminal MTJ Memory Cell with Read Disturb Immunity (U. of Toronto)
  • 5.1.3 Time Differential Sense Amp for 40 nm STT MRAM (Infineon, TU Munich)
  • 5.3 Decreasing Switching Current Density and Write Power in an STT-MRAM
  • 5.3.1 Low Vth STT-RAM Select Transistor (U.Virginia, Amer.U.Beirut, Intel)
  • 5.3.2 Techniques for Lowering Write Power in STT-MRAMs (Karlsruhe IT)
  • 5.3.3 Using Current Asymmetry in STT-MRAM to Reduce Write Power (Karlsruhe IT)
  • 5.3.4 Low Energy Write STT-MRAM With Dynamic Data Encoding (Penn State U, Qualcomm)
  • 5.3.5 Low Current Probabilistic Write for STT-MRAM (U Calif. SD, Qualcomm, George MasonU)
  • 5.4 Source Degeneration Effect and Current Asymmetry Issue in STT MRAM
  • 5.4.1 Overview of Source Degeneration and Current Asymmetry in STT-MTJ
  • 5.4.2 Reduced Power and Improved Margins Using Asymmetric FET (Purdue, Penn St)
  • 5.4.3 STT-RAM Design to Read and Write at Similar Voltages (Spintec, CEA-INAC, Crocus)
  • 5.4.4 Multi-Terminal MRAMs to Compensate for MTJ Asymmetry Effects (Purdue U.)
  • 5.5 Thermal Stability Issues in STT MRAM
  • 5.5.1 Statistical Study of STT-MRAM Thermal Stability (Infineon)
  • 5.6 Current vs. Voltage Drive Write
  • 5.6.1 STT-MRAM Write Using Current Sources to Reduce Energy (IBM, Purdue)

6.0 Multiple Level/State STT-MRAM

  • 6.1 MLC STT-MRAM Using Serial & Parallel Cell (Penn State U, Qualcomm)
  • 6.2 Fast Read 1T2MTJ MLC STT-MRAM with Stacked Perpendicular MTJ (LEAP)

7.0 Domain Wall STT MRAM Cell Technology

  • 7.1 Domain-Specific Multicore Computing Using Spin Memory (Purdue U. and Intel)
  • 7.2 Multi-Level MRAM using Domain Wall Shift for a High Density Cache (Purdue U.)
  • 7.3 FeCo-Oxide as a Magnetic Coupling Layer in an mLogic Cell (Carnegie Mellon U.)
  • 7.4 Multi-Level MRAM Cell Based on Domain Wall Shift Storing 2b per Cell (Purdue U.)
  • 7.5 DW Motion MRAM With PMA (Renesas, Tohoku U., NIMSA Tsukuba)
  • 7.6 Domain Wall Memory with Shift Based Writes for Use in a Cache Hierarchy (Purdue U.)

8.0 Racetrack Type Domain Wall Memory-Logic

  • 8.1 Multilane Racetrack with Compression & Independant Shift (U.Pittsburgh, VMware)
  • 8.2 Logic-in-Memory Operation in PMA Domain Wall Nanowire Devices (Kyushu U.)
  • 8.3 Racetrack STT MRAM Memory for Cache Applications (Broadcom)
  • 8.4 Domain-Wall Nanowire Memory for Memory and Logic (Nanyang TU)
  • 8.5 STT Driven Magnetically Coupled DW Shift Register memory (Carnetie Mellon U.)
  • 8.6 Magnetic Adder based on a Vertical Racetrack Memory (U. of Paris-Sud, UMR8622m CNRS)

9.0 Three Terminal STT-MRAM Mechanism and Cells

  • 9.1 Compact Model of 3 Terminal MRAM Switching (SPINTEC, UNR, INAC, CEA/CNRS/UJF)
  • 9.2 Complementary Polarizer Cell to Improve Sense Margin and Read Disturb (Purdue U.)

10.0 MRAM with Spin Transfer Write and Perpendicular Anisotropy

  • 10.1 Potential for Reduction of Energy Consumption in P-MRAM (Toshiba)
  • 10.2 Sub 20 nm p-MTJ Stack for Standalone and Fast Embedded Memory (IMEC)
  • 10.3 Challenges for Developing Terra-bit p-STT MRAM (Hanyang U., Samsung)
  • 10.4 Embedded STT-MRAM Cache Memory using p-MTJ to Reduce Power (Toshiba)
  • 10.5 Switching Current Dispersion from Inhomogeneity of PMA (TsinghuaU., PekingU, CICQM)
  • 10.6 PMA STT-MRAM with sub 5 ns Write and No Degradation at Temperature (NVMTS)
  • 10.7 Microwave Properties and Damping in Pt/Co Multilayers with PMA (INRM, Korea U.)
  • 10.8 Switching Properties in MTJ with Interfacial PMA (U. of Calabria, U. Messina)
  • 10.9 Scaling of In-Plane and PMA MTJ Using a Physics-Based Model (Univ. of Minnisota)
  • 10.10 8Mb Perpendicular STT-MRAM Prototype with sub-5ns Write (TDK-Headway)
  • 10.11 Multi-Level Perpendicular MTJ with Multiple Barrier Free Layers (LEAP)
  • 10.12 <1ns Switch & <20nm Scaling (SPINTEC, UMR, CEA/DSM/INAC-CNRS/UJF-G-INP, Crocus,
  • 10.13 A Top Pinned PMA MTJ with Counter Bias Field to Suppress Stray Field (LEAP)
  • 10.14 Optimization of Co/Pd Multilayer-based Reference Layers in p-MTJ (IBM)

11.0 Topics and Issues in Perpendicular MTJ MRAM

  • 11.1 Scaling of Perpendicular MTJ MRAM
  • 11.1.1 Scaling of i-PMA STT-MRAM below 15 nm with Damage-less Patterning (Samsung)
  • 11.2 Process Related Factors in i-PMA STT MRAM
  • 11.2.1 Embedded Perpendicular STT-MRAM Made After BEOL Process (Toshiba)
  • 11.3 Thermal Stability Factor in Perpendicular CoFeB/MgO MTJ MRAM
  • 11.3.1 Area Dependence of Thermal Stability in p-STT MRAM (LEAP)
  • 11.3.2 STS of pMTJ CoFeB-Based Tunnel Junctions with High Thermal Tolerance (Sony)
  • 11.4 Co/Pd Multilayer Reference layers in p-MTJ (IBM-Headway Alliance and IBM)
  • 11.5 In-Plane vs. Perpendicular Magnetization
  • 11.5.1 Roadmap of Planar & Perpendicular STT-MRAM (U. of Minnesota, NUS)

12.0 Voltage Controlled (VCMA) PMA MRAM

  • 12.1 Low Power Write and Sense Amp for Fast VCMA MRAM (UCLA)
  • 12.2 Voltage Controlled Magnetic Anisotropy MeRAM Cell (U. of Calif. LA, Inston)
  • 12.3 Voltage Driven Magnetization Switching (AIST, Osaka U.)

13.0 Simulation and Modeling of Spin Write MRAMs

  • 13.1 Optimized Resistance Characterization Technique for MRAM (A*STAR)
  • 13.2 Circuit-Level Model for Temperature Sensitive Read/Write in MTJ (Ewha Womans U)
  • 13.3 Analytical Macrospin Model of STT-MTJ Switching Time (U. Paris-Sud)
  • 13.4 Integration of STT-MRAM Model into CACTI Simulator (Politec, di Torino)
  • 13.5 Switching Current Dispersion from Inhomogeneity of PMA (TsinghuaU., PekingU CICQM)
  • 13.6 Survey of Models of MTJ (U. of Toronto)
  • 13.7 Modeling MTJ with Vertical Access Devices for Mixed Mode Simulations (IIT Roorkee)
  • 13.8 Study of Electrical Simulator Models for Spintronic Devices (INAC-SPINTEC)
  • 13.9 Microstructure Processing and Simulations of MTJ MRAM (IBM)
  • 13.10 Modeling of Spin-Based Electronic Devices (TU Wien)
  • 13.11 Unified Model for Switching Behavior of MTJs (Ewha Womans University)
  • 13.12 Model for TDDB of MgO in MTJ-MRAM Cell (Purdue)
  • 13.13 SPICE Compact Model for Simulating Hybrid MTJ/CMOS Circuits (Purdue U.)
  • 13.14 Simulation for STT-MRAM with Multiferroic Tunnel Junctions (Purdue U.)
  • 13.15 Multi-level STT MRAM Cell Based on Stochastic Switching (U. Paris-Sud)
  • 13.16 Modeling of Stochastic STT Write in MTJ (U. Paris-Sud, UMR, SPINTEC, CEA/CNRS)
  • 13.17 Simulated Characteristics of Lateral TMR Memory Cell (Peking U., Tsinghua U.)

14.0 Test, Yield and Reliability Issues for STT- MRAM

  • 14.1 4-Point Probe Ramped Voltage Stress for STT-MRAM MgO TJ (IMEC, KU Leuven)
  • 14.2 Unified Design Framework to Enhance Yield of STT-MRAM (Purdue Univ.)
  • 14.3 Robustness Margin for Read/Write of STT-MRAM Cell (Polit. di Tornio)
  • 14.4 Wafer Inductive Measure of STT Critical Current Density, (Phys.-Tech Bundesanstalt,
    Intl. Iberian Nanotech Lab., INRM Turin, AGH U. of Sci. and Tech., Bielefeld U., Singulus)
  • 14.5 Yield and Reliability Techniques for Improving STT-MRAM Production (Beihang U.)
  • 14.6 Radiation Hardened Sensing Circuits for STT MRAM and Logic (U. of Paris-Sud)
  • 14.7 Soft Error Tolerant MRAM Latches (Sharif Univ. of Tech.)
  • 14.8 Block-Level Reliability Estimation for STT-MRAMs (Politechnico di Torino)
  • 14.9 Read Disturb Circuit Detect Method in STT-MRAM (Karlsruhe IT)
  • 14.10 Test Support for MRAM Cell Development Defect Monitors in a Lab (IBM)
  • 14.11 Heavy Ion Irradiation of Perpendicular Anisotropy CoFeB-MgO MTJ (JAXA)
  • 14.12 OS-MLS codes for Multi-Bit Error Correction in STT-MRAM (Beihand Univ.)
  • 14.13 Advantages of Strong Error Correction for Unintended Bit-Flips (U. of Minnesota)
  • 14.14 Failure Mitigation Techniques for 1T-1MTJ STT-MRAM Cells (Purdue U.)
  • 14.15 Testing Resistive-Open Defects in TAS-MRAM (Crocus, LIRMM, U. Montpellier, CNRS)
  • 14.16 Reducing Read Disturb using Pulse Width Control for in-plane STT MTJ (Avalanche)
  • 14.17 Switching Failure From Transverse Domain Wall Formation in FL (TU Wien)
  • 14.18 TDDB of the MgO for an STT-MRAM (Purdue U.)
  • 14.19 STT-MRAM in 65 nm LP-CMOS with Radiation Results (U. Albany, Avalanche)

15.0 Spin Orbit Torque (SOT) Devices

  • 15.1 Analysis of SOT-MRAM for On-Chip Cache Hierarchy (Karlsruhe Inst. of Tech.)
  • 15.2 Compact Model of Three Terminal SOT MTJ writing (Spintec)
  • 15.3 Spin-Orbit Torque (SOT) MRAM Cell (U. of Calif. LA, Inston)
  • 15.4 Compact MTJ Model for Spin Orbit Torque (SPINTEC, UMR, INAC, CEA/CNRS/UJF)
  • 15.5 SOT-MRAM Benefits Compared with SRAM in L1 and L2 Cache (Karlsruhe IofT)
  • 15.6 Rashba-Induced Spin Torque Switching
  • 15.6.1 Using Rashba Effect for Write & Read in a Single FM Layer (NUS)
  • 15.7 Spin Hall Effect With Spin Torque Switches
  • 15.7.1 Dual Read/Write Ported Spin-Hall MRAM for On-chip Cache (Purdue University)
  • 15.7.2 Analog Readout Circuit for Use with Planar Hall-Effect MRAM (Bar-Ilan U.)
  • 15.7.3 Spin Hall Effect in Fast Current Mode Spin-Torque switches. (Purdue U.)
  • 15.7.4 Differential Spin-Hall Embedded MRAM (Purdue U.)

16.0 Thermal Assisted, Magnonic Write and Thermal Transport in MRAMs

  • 16.1 Analysis of MTJ/CMOS Hybrid Cells Using TAS and STT(U.Montpellier)
  • 16.2 Analysis of Resistive-Open Defects on TAS-MRAM Behavior (LIRMM, Crocus)
  • 16.3 TAS Programming in STT-MRAM Systems (LIRMM-UMR CNRS, Crocus)
  • 16.4 Effect of Heating Current Polarity on TAS Switching in MRAMs (SPINTEC, Crocus)
  • 16.5 Thermally Activated VCMA MeRAM Cell (U. of Calif. LA, Inston)
  • 16.6 Thermal Assisted MRAM Production (Crocus)
  • 16.7 Logic Functions of TA-MRAMs (SPINTEC CEA-INAC/CRNS/UJF/G-INP, Crocus )
  • 16.8 TA-STT Magnetic Reversal of Uniaxial Nanomagnets in Energy Space (N.Y.Univ.)
  • 16.9 Temperature Dependence of Jo for STT TA-MRAM using GdFeCo(Nagoya U, NISRI
  • 16.10 MTJ Storage & Logic Unit Using Thermally Assisted MRAM (Crocus, SPINTEC)
  • 16.11 Storing Data in Antiferromagnetic Layer Via Field-Cooling (Politechnico di Milano)
  • 16.12 Theory of Bidirectional Write Thermoelectric STT-MRAM Using Magnonic Current

17.0 Vertical 3D MRAMs.

  • 17.1 3D STT-MRAM Transistor-less Cell Array (U. of Wisconsin)
  • 17.2 Dual Function STT-MRAM for Reliability and 3-D MLC (U. Paris-Sud, CNRS, U. Beihang)
  • 17.3 MRAMs in Cross-Point Arrays
  • 17.3.1 Diode-MTJ Cross-Point Memory Using Unipolar Switching (U.of Calif,Hitachi, Singulus)

18.0 Field Assisted Switching MRAMs

  • 18.1 Electric Field Assisted Switching in MTJ
  • 18.1.1 Electric Field Controlled Switching in PMA MRAM (A*STAR)
  • 18.1.2 Reducing Latency in STT-MRAM Using Field Assisted Writing (U. of Rochester)
  • 18.1.3 Electrical Field Assisted Switching in MTJ (Polit.Bari, CalabriaU, PerugiaU, MessinaU)
  • 18.2 Field Assisted Toggle Mode Switching
  • 18.2.1 Neutron Radiation Effect on Toggle Mode MRAM (LIRMM, U. de Montpellier)
  • 18.2.2 Write Current Self-Configuration Method (NTHU)

19.0 MTJ MRAM Materials and Device Research Issues

  • 19.1 Straintronics Based MRAM for Data Storage (U. of Michigan)
  • 19.2 Asymmetric Composite Free Layers for High Density STT-MRAM (Kyushu U.)
  • 19.3 Magnetic Field Dependence of Energy Barrier of p-Magnet (Korea U., Samsung)
  • 19.4 Magnetic Properties of Thin Seed Layers of Ru & Hf on Co/Pt MLs (IMEC, KU Leuven)
  • 19.5 A Study of Coupled Spin Torque Nano Oscillators (U. of Virginia)

20.0 Graphene, Nanoribbons and Edge Conductors in Spin Devices

  • 20.1 Graphene Based MTJ (Naval Research Lab)



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