Memory Strategies International

Semiconductor Memory Services

 
| Home | Reports | Consulting | Contact | About

Purchase Report

Technology & Applications for Embedded MRAM, March 2018

As CMOS technology scales into the 2X and 1X geometries, new memory technologies are needed. It appears that the MRAM, probably in its current pMTJ STT-MRAM form is a serious contender for use in many applications in these high technology geometries. Attributes of the p-STT-MRAM are non-volatility, nearly unlimited endurance, fast switching at low voltages and CMOS wafer fab compatibility. The technology is tunable between high speed and low power applications. Several startups are developing standalone MRAMs hoping to compete with SRAMS, Flash and provide persistent DRAM. At least three major foundries are expected to be in production in the 2018-2020 time-frame with embedded p-STT-MRAMs intended for integration into 20-28nm CMOS technology. Applications under consideration include: replacing eSRAM in level 2 and 3 cache and replacing eDRAM in LLC., using the p-STT MRAM as OTP to replace fuse and trimming devices on SoC chips already using the STT-MRAM for embedded memory, using STT-MRAM as look up tables (LUT) or as CAMS and search engines, using STT-MRAM as embedded unified memory replacing both the SRAM working memory and NOR Flash/ EEPROM NVM currently used in industrial MCU and SoC chips, using MRAM in neumorphic and brain-type chips, using MRAM for high density mostly-off data storage systems, and using MRAM in security devices, such as PUFs. The many issues with getting the p-STT-MRAM technology into volume production in the CMOS wafer fab are being studied and reliability studies are being reported.. Tool kits for design and development of SoC and MCU using embedded MRAM are being offered by foundries and design courses in MRAM are being offered. High temperature applications such as automotive are beginning to be addressed.

90+ pages.

Technology & Applications for Embedded MRAM, March 2018

Table of Contents


I. MRAM Technology development

1.1 Brief Background on Historical MRAM Technology

1.2 STT-MRAM Technology Development

  • 1.2.1 STT-MRAM cell design with partial source line planes
  • 1.2.2 STT-MRAM Using 3D Vertical Nanowire GAA High-k Select Device
  • 1.2.3 Self-Reference Read for 2T2MTJ STT-MRAM static gain cell
  • 1.2.4 Security and Privacy Threats to on-chip NVM
  • 1.2.5 Failure Mechanisms and Testing of embedded STT-MRAM arrays
  • 1.2.6 TMR Dependent Switching Behavior of STT-MRAM
  • 1.2.7 MTJ Film Underlayer Effect on STT-MRAM TMR & Retention
  • 1.2.8 Error-Free Sense Amplifier for Use with STT-MRAM.
  • 1.2.9 Effect of TMR on STT Switching in Magnetic Tunneling Junctions

1.3 Perpendicular STT-MRAM Technology Development

  • 1.3.1 Overview of p-STT MRAM Technology Development
  • 1.3.2 Reduction of Programming Current Using P-STT-MRAM
  • 1.3.3 Using p-STT-MRAM to Replace SRAM in Level 2 and Lower Cache
  • 1.3.4 Reliable 1Gb pMTJ in 28 nm Logic for emb pSTT-MRAM
  • 1.3.5 Ta spacer Oxygen scavenging in CoFeB free layer in pMTJ
  • 1.3.6 Analysis of sub-20nm p-MTJ for Use in the Cache Hierarchy
  • 1.3.7 Using p-STT MRAM in LLC Cache with Error-Free Sub-ns Switching
  • 1.3.8 Reliability Study of Perpendicular STT-MRAM
  • 1.3.9 Improved Reference Layer in Stack for p-MTJ MRAM
  • 1.3.10 Scalability of p-STT-MRAM in <10nm CMOS in 1Gb Arrays
  • 1.3.11 8Mb p-STT-MRAM Macro in 28 nm CMOS Logic
  • 1.3.12 Modeling of Magnetic Coupling between Adjacent Bits in Dense MTJ
  • 1.3.13 pSTT-MRAM Manufacturability in 2X CMOS
  • 1.3.14 pSTT-MRAM Op.with Ext. Mag. Field afterr 260 C Solder Reflow
  • 1.3.15 Switching Efficiency of 400 C Compatible p-MTJ MRAM
  • 1.3.16 Analysis of Magnetic Properties of pMTT-MRAM in sub-20 nm range
  • 1.3.17 Nanopatterning Narrow Pitch p-MTJ Stacks for Dense MRAMS .
  • 1.3.18 BEOL Compatibility for Top-Pinned MTJ Stack
  • 1.3.19 1Mb 28nm STT-MRAM with new Sense Amp and Self Write

1.4 Domain Wall MRAM

  • 1.4.1Domain Wall Fast Switching in High Capacity pSTT-MRAM

1.5 Spin-Orbit Torque Mechanism

  • 1.5.1 Overview of Spin orbit Torque Mechanism
  • 1.5.2 Spin Orbit Torque eMemory for sub 14 nm CMOS

2.0 Applications for STT-MRAMS

2.1 Overview of Applications for STT-MRAM Standalone and Embedded

2.2 Applications for Embedded MRAMS in Cache Memory

  • 2.2.1 Using eMRAM in High Level Cache
  • 2.2.2 2T2MTJ Gain Cell in Cache Memory Application
  • 2.2.3 Using eMRAM in the Memory hierarchy of MCU Chips
  • 2.2.4 PE Tradeoffs for STT-MRAM & SRAM Caches
  • 2.2.5 Cache Replacement Algorithm for L2 STT-MRAM Cache
  • 2.2.6 eSTT-MRAM cache at sub-3 ns pulses in sub-20 nm eSTT-MRAM
  • 2.2.7 Perpendicular Anisotropy in <30 nm MRAM devices for LLC
  • 2.2.8 Fine Grained SRAM-STT-MRAM Hybrid Cache Memory System

2.3 STT-MRAM Use as OTP

  • 2.3.1 STT-MRAM Conversion to OTP

2.4 MRAM as Look-up Tables (LUT)

  • 2.4.1 MRAM in Processing Elements using Look-Up Tables

2.5 MRAM as CAMs and Search Engines

  • 2.5.1 CAM Operation using SOT MRAM

2.6 STT-MRAM in High Performance Mobile Embedded Memory Devices

  • 2.6.1 MPSoC using Dynamic Reconfiguration for Mobile Devices
  • 2.6.2 DSPs for SmartPhones and IoT using Domain Wall Memory

2.7 Embedded STT-MRAM for High Performance Memory Applications

  • 2.7.1 Obstacles to Embedded MRAM in High Performance CMOS MCU
  • 2.7.2 Analysis of MRAM in High Performance Embedded Applications
  • 2.7.3 2T2MTJ 32Kb eSTT-MRAM with 1.3 nm Tac for Fast Circuits

2.8 STT-MRAM as Unified Embedded Memory.

  • 2.8.1 A Unified eMemory Using 40 nm 1Mb p-STT-MRAM

2.9 STT-MRAM in Low Standby Power Portable Devices

  • 2.9.1 pSTT-MRAM in Low Standby Power IoT and Wearables

2.10 MRAM in Neuromorphic and Brain Chips

  • 2.10.1 Brain-Inspired Chips Using Spintronics Technology

2.11 High Density Data Storage STT-MRAM

  • 2.11.1 Sense Amps for High Density Near Zero Standby Power Data Storage

2.12 STT-MRAM for Fast, High Density Embedded Memory Applications

  • 2.12.1 STT-MRAM 40 Mb Array in 2x nm eNVM in GP and MCU
  • 2.12.2 High Density High Performance Embedded gMRAM

2.13 STT-MRAM for Normally-OFF Computing Systems

  • 2.13.1.1STT-MRAM for NV Systems with Normally-OFF Computing and Checkpoint.Rollback

2.14 STT-MRAM in Security Devices (PUF)

  • 2.14.1 Using a p-STT-MRAM for PUF in IoT Security
  • 2.14.2 MRAM PUF for System Security

2.15 Fast and Dense MRAM for DRAM SCM Replacement

  • 2.15.1 3D Cross-point 1T-1STT-MRAM for Dense DRAM Replacement as SCM

2.16 MRAM as universal Memory Integrated Seamlessly into Processor Systems

  • 2.16.1 Using MRAM as a Universal Memory In Processor Systems

3.0 Commercial MRAM Development and Production

3.1 Overview

3.2 MRAM Start-ups

  • 3.2.1 Everspin Technologies
  • 3.2.2 Spin Transfer Technology (STT)
  • 3.2.3 Avalanche Technology

3.3 MRAM Foundries

  • 3.3.1 TSMC
  • 3.3.2 Globalfoundries
  • 3.3.3 Samsung

Bibliography

Back to Top

To Order "Technology & Applications for Embedded MRAM, March 2018"

Select:

For more information, please Contact Memory Strategies

 
Memory Strategies International, 16900 Stockton Drive, Leander, TX, USA 78641; 512 260 8226; Copyright (c) 2020 Memory Strategies International. All rights reserved. Privacy.