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Memories in Neuromorphic and Deep Computers and Big Data Search Engines, April 2017

A number of neuromorphic systems have been demonstrated using variable resistance memories as synapses connecting neuron-like devices. Various applications today have been demonstrated using neuromorphic systems with resistance RAM synapses. These include: facial recognition, character recognition, voice recognition, parallel dictionary learning and many other similar systems. These categorization type learning systems can be implemented at a chip level and have the potential to be useful in Smart IoT Networks in analyzing data inputs from the network and learning from them. Particularly in "edge of the Internet" networks, local analysis of data can be tailored to the specific application by such a system. A wide variety of resistance RAM memory devices have been studied for this application. These include: Metal Oxide ReRAM, Conductive Bridge RAM (CB-RAM), Phrase Change Memory (PCM), Ferroelectric RAM (FeRAM), Magnetic RAM (MRAM), Charge Trapping NVM, and various polymer flexible memories intended for use as wearable computers. Cloud based applications can benefit from large search engines such as T-CAMs. Deep learning processors targeting embedded perception and cognition are advancing significantly. These highly integrated next-generation processing systems are being developed and several recent developments of deep neural network engines are discussed in this report.

100+ pages.

Memories in Neuromorphic and Deep Computers and Big Data Search Engines, April 2017

1.0 Overview of Memories as Neuromorphic Computers and Big Data Search Engines

2.0 Overview of Neuromorphic Systems

3.0 Neuromorphic Systems Using Resistance RAMs

3.1 Neuromorphic Systems Using Metal Oxide and Conductive Bridge RRAMs

  • 3.1.1 Neural Networks Using Resistive Memory (CEA-LETI, CEA-LIST, INRIA)
  • 3.1.2 Evolving Spiking Networks with Variable Resistive Memories (U. West of England)
  • 3.1.3 RRAM Synaptic Device for Neuromorphic Computing (Postech, Gwangju IST)
  • 3.1.4 2-Terminal Resistive Devices for Neuromorphic Computing (ASU, Stanford, U of Penn.)
  • 3.1.5 RRAM for Binary and Analog Synapses in Neuromorphic Computing (ASU)
  • 3.1.6 3-D Vertical Analog Switching RRAM for Neuromorphic Computing (U of Michigan)
  • 3.1.7 ReRAM Cross-point Array for Parallel Dictionary Learning (Arizona State U.)
  • 3.1.8 Suppressing Intrinsic Variations in Metal-Oxide Synaptic RRAMS (Peking U.)
  • 3.1.9 3D Synaptic Device using a Ultralow Energy ReRAM (NCTU)
  • 3.1.10 Neuromorphic Pattern Learning using ReRAM Electronic Synapse (NCTU)
  • 3.1.11 Cell Classifier for RRAM Process Development (Uof Southampton, Imperial C. London
  • 3.1.12 Tracing Brain Memory to ReRAM Neuromorphic Systems (CEA LETI)
  • 3.1.13 Neuromorphic Hybrid ReRAM/CMOS Synapses (P.diMilano, IUNET)
  • 3.1.14 Oscillatory Neural Networks Using Multilevel RRAMs (Carnegie Mellon)
  • 3.1.15 RRAM-based Neuromorphic System for Vision Systems (Stanford)
  • 3.1.16 General Model for Voltage Controlled Memristors (Stanford, Israel IoT, U. Rochester)
  • 3.1.17 Electronic Synapse Device Using Multilevel CB-RAM (China/Taiwan U)
  • 3.1.18 HfO2 RRAMs as Synapses for Convolutional Neural Networks (CEA-LETI)
  • 3.1.19 Advantages of RRAM Crossbar Arrays in Matrix Multiplication (Sandia labs)
  • 3.1.20 Restricted Boltzman Machine Using Stochastic RRAM Effects (IEF- IEMN-CNRS)
  • 3.1.21 1T1R RRAM Neuromorphic Network for Pattern Classification (Tsinghua U)
  • 3.1.22 RRAM Variability for Extreme Learning Machine Architectures (IIT New Delhi)
  • 3.1.23 Learning for Grayscale Image Recognition in RRAM System (Peking U., Sandisk)
  • 3.1.24.Simulated Neuromorphic Network using Vertical RRAM Cells (French Labs)
  • 3.1.25 Mo/PCMO Analog Synapse and IMT Oscillator Neuron (POSTECH)
  • 3.1.26 Neuromorphic Learning using a Bistable 1T1R MO RRAM Synapse (PdiMilano)
  • 3.1.27 Issues with Partitioning SRAM & RRAM Synaptic Arrays (Arizona State U)
  • 3.1.28 Neuromorphic Computing with Hybrid RRAM-CMOS Synapses (Pdi Milano, IU.NET)
  • 3.1.29 Spike Timing Dependant Plasticity Shown in in CBRAM (Arizona State U)
  • 3.1.30 Vertical Pillar CBRAM for Neuromorphic Applications (CEA.LETI, IM2NP, IMEP LAHC)
  • 3.1.31 Analog RRAM Neural Net with Online Gradient Descent Training(Israel IT, Columbia U)
  • 3.1.32 1T1R RRAM Synapse for Handwriting Digit Classification (Pdi Milano, IU.NET)
  • 3.1.33 Neural Network Simulated Neurons & Hardware CBRAM (Pohang UofS&T)
  • 3.1.34 4-Layer Vertical RRAM Integrated with FinFET (Stanford U., NARLabs))
  • 3.1.35 Multilevel Synaptic Characteristics in a Resistive Memory (POSTECH)
  • 3.1.36 Power Efficient Structure for RRAM Convolutional Neural Networks (Tsinghua U.)
  • 3.1.37 Synaptic behavior of RRAM with AG Nanoparticles on Flexible Substrate (Fudan U)
  • 3.1.38 Identical Pulses to Improve RRAM Synaptic Behavior (POSTECH)
  • 3.1.39 Implementation of Bilayer 3D RRAM Cross-bar Array (U. of Calif. Santa Barbara)
  • 3.1.40 Large ReRAM Array Design for Neuromorphic Computing (IBM, POSTTECH, EPFL)
  • 3.1.41 Linear Potentiation Optimized Programming in HfO2 RRAM Synapse (POSTECH)
  • 3.1.42 RRAM Unsupervised Learning Boltzmann Machine (Stanford, U. Calif., IBM Macronix)
  • 3.1.43 RRAM Volatility Characterization for Neuromorphics (U. Southampton, IC London)
  • 3.1.44 TiOx ReRAM with 64 Conductance levels for Synapse Applications (POSTECH)
  • 3.1.45 Oxide-Based Analog Synapse Characterization (TshinguaU, PekingU, SouthernUST)
  • 3.1.46 Binary RRAM Neural Net for Classification & Training (Arizona S.U., TsinghuaU)
  • 3.1.47 Synaptic Plasticity using OxRAM with Noisy Input Data (French labs)

3.2.0. Neural Network Systems Using FeRAM Technology

  • 3.2.1 3-Terminal Ferroelectric Memory for On-Chip Pattern Recognition (Panasonic)
  • 3.2.2 Fabrication of Synapse Chips Using 3T-FeMEMs in CMOS Logic (Panasonic)
  • 3.2.3 Synapses Using 3T-FeMEM for Multishaded Image Recognition (Panasonic)
  • 3.2.4 STDP Circuit using Ferroelectric Tunnel Memrister (Univ.Paris-Sud, Beihang U)
  • 3.2.5 Synaptic Plasticity in FeFET Conductance (E*T Research I, Hanbat Nat U., Dongguk U.)
  • 3.2.6 Ferroelectric Info Processing using Multivalued Logic (Argonne, LilleU, UPJV)

3.3 Neuromorphic Memories Using Polymer and Flexible Memories

  • 3.3.1 Synaptic Behavior in Flexible IZO FET on Plastic Substrates (Nanjing U, CAS)
  • 3.3.2 Organic CoPolymer RRAM as Synapse in Neuromorphic System(CNR-IMEM)
  • 3.3.3 Evolving Spiking Networks with Variable Resistive Memories (U. West of England)
  • 3.3.4 Polymer RRAM for Neuromorphic Applications (E. China UST, CAS, FudanU)
  • 3.3.5 Organic Memristors in Neuromorphic Networks as Analogs of Synapses (UParma)
  • 3.3.6 Organic Neuromorphic for Human-Machine Interface.(U. Minnisota, GwangjuIST)
  • 3.3.7 Organic NM with 500 distinct states (Stanford, U.Groningen, SandiaNL, U.de Sao Paulo)

3.4 Early Neuromorphic Chips architecture Using FPGA

  • 3.4.1 Neuromorphic chip for efficient computation (Georgia Institute of Technology)

3.5 Neuromorphic Computers Using Phase Change Memory (PCM)

  • 3.5.1 2-PCM Synapse Neuromorphic Architecture (CEA-LETI)
  • 3.5.2 2-PCM Synapse in Large Neuromorphic System (CEA-LIST, CEA-LETI, MINATEC)
  • 3.5.3 Array-Level Learning with PCM Synaptic Devices (Stanford, U of Penn, IBM)
  • 3.5.4 Neural Network Using Two PCM Devices for Weight of each of 164,885 Synapses(IBM)
  • 3.5.5 Non-von Neumann Arithmetic Processing Using PCM Cells (Oxford, Exeter, IBM)
  • 3.5.6 PCM Synaptic Array with On-Chip Neuron Circuits for Continuous Learning (IBM)
  • 3.5.7 Use of PCM in Brain-inspired Neuromorphic Systems (IBM, Macronix)
  • 3.5.8 PCMO Synaptic Devices
  • 3.5.8.1 PrCaMnO3 (PCMO)-Based Synaptic Devices (Pohang UST, Gwangju IST, IBM)
  • 3.5.8.2 Analog Synapse using 5-bit MLC PCMO (Pohang UST, GwangjuIST, IMEC)

3.6 SST MRAM in Neuromorphic Memory

  • 3.6.1 STT MRAM as a Stochastic Memristive Synapse (U. Paris-Sud, CNRS, CEA, LIST)
  • 3.6.2 STT MRAM as Synapse for Neuromorphic Systems(U. Paris-Sub, CEA, Beihang U.)
  • 3.6.3 Spin Memory Devices with Matching and Self-Reference Function (Avalanche)
  • 3.6.4 Neural Network Using Spintronic Synapse & Neuron (Beihang,Paris-Sud, Tsinghua)

3.7 Other Neuromorphic Memory Devices

  • 3.7.1 A Synapse Using Si-Based Charge-Trap Memory (Seoul Nat. U., Samsung)
  • 3.7.2 CMOS Compatible Si-based Oscillator and Threshold Switch (Carnegie Mellon)

4.0 Big Data Search Engines and Look-up Tables

4.1 TCAMs and Search Engines

  • 4.1.1 256bit Wordlength 2.5T1R ReRAM TCAM in CMOS Logic (NTHU, TSMC, NCTU)
  • 4.1.2 Spintronics CAM Using Spin-Orbit-Torque Programming (Avalanche Tech.)
  • 4.1.3 3T1R nvTCAM MLC ReRAM with <1 ns Search Time (NTHU, ITRU, NCTU)
  • 4.1.4 nvLUT with ReRAM for Reconfigurable Logic (ITRI, Nat. Taipei U., NTHU, Min Shin U.)
  • 4.1.5 4T2R ReRAM in TCAM for Big Data Processing (NTHU, NCTU, NDL, ITRI)
  • 4.1.6 RRAM Crossbar Array for Matrix Vector Multiplication (Tsinghua U, Arizona SU)
  • 4.1.7 Hybrid Cloud Storage of RRAM & TLC NAND Flash with RAID-56(Chuo U, UofTokyo)
  • 4.1.8 ReRAM Cross-bar Array Memory System Characteristics (Oakridge National Lab.)

4.2 Deep Learning Systems

  • 4.2.1 2.9 TOPS/W Deep Convoluational Neural Net 28nm SoC (ST Micro)
  • 4.2.2 8.1 TOPS/W Reconfigurable Processor for Deep Neural Nets (KAIST)
  • 4.2.3 28 nm SoC with 1.2 GHz Sparse Deep NN Engine for IoT
  • 4.2.4 Speech Recognizer with Deep Models and Power Gating (MIT)
  • 4.2.5 0.26-10 TOPS/W subword parallel NN Processor in 28 nm FDSOI (KU Leuven)
  • 4.2.6 0.52mW Convolutional NN Face Recognition Processor and a Face Detector (KAIST)
  • 4.2.7 288uW Programmable Processor with non-Uniform Memory Hierarchy (U.Mich.,Cubeworks)
  • 4.2.8 135 mW Integrated data processor for sequencing (Nat. Taiwan U)

Bibliography

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