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Developments in Non-Volatile Embedded Memories, March 2019
(RRAM, CB-RAM, PCM, FeFET, FRAM, MRAM, CT, Organic, Foundries)

As traditional “emerging memories” enter our modern wafer fabs with their new materials and processes, a burst of innovation in embedded emerging memories has appeared. For RRAMs, now entering production, attention is turning to reliability issues and the effect of physical characteristics on retention and endurance. Ultralow power, density and timing characteristics are becoming more important. Embedded Conductive Bridge RAMs (CBRAMs) are trending into high reliability applications such as automotive so that materials and memory configuration are more critical. Embedded Phase Change Memory (PCM) is being used in various technologies for its dense memory and CMOS independence. ePCM is being considered in smart power BCD technology, merged into DRAM hybrids and in Bipolar CMOS/DMOS. The ferroelectric and charge trapping properties of the HfO2 common in modern wafer fabs has led to a burst of studies using HKMG FeFETs, HfZrO NVMs, nvSRAM using Fe-HfO2 capacitors, and dual Charge Trapping (CT) memories and FeMEMs used at different voltages. As the large foundries have standardized on the perpendicular MTJ STT-MRAM for embedded non-volatile memory for many applications the MRAM has become a mainstream embedded memory with process engineering, testing and reliability moving to the forefront of developmental efforts. eMRAM processes are offered that can be tweaked for low power or high speed. FD-SOI eMRAM for low power automotive is showing zero failure after 1M endurance cycles, a low damage MTJ integration process has shown 1010 cycles endurance along with 10 year retention. Process optimization efforts are showing TMRs near 300%. Industrial applications are developing as eMRAM becomes common. Efforts have turned to using MRAM building blocks for derivative NVM devices such as OTP, PUF, & RNG. MRAM is being used for data cache for mobile devices, and for nvFF and nvSRAMs. New materials for charge trapping eNVM are being investigated including graphene oxide Quantum Dots in high K materials. TFT CT eNVM are used in flat panel displays and In2O3 nanoparticle RRAMs are in development. FinFET split-gate MONOS is used in automotive applications. The split gate eFlash cell continues to be developed and used for automotive applications and for worst case conditions integrated with copper and low -K interconnects. Embedded NVM using logic transistors only is proposed in dense logic with nearly competitive cell size and no CMOS process modifications. It is expected that the current burst of innovation in embedded NVM in new wafer fab materials and options will continue for some time.

125+ pages.

Developments in Non-Volatile Embedded Memories, March 2019
(RRAM, CB-RAM, PCM, FeFET, FRAM, MRAM. CT, Organic, Foundries)

Table of Contents

1.0 Introduction to Embedded Non-Volatile Memories

2.0 Embedded Resistive RAM (RRAM)

  • 2.1 Study of MOSFET degradation due to high Vds in sub-28 nm Technology (Zhejiang U.)
  • 2.2 Ultra-Low Power Atom Switch (RRAM) for Use in NV SoC (NEC)
  • 2.3 16Mb Dual-Mode RRAM with <1.4 ns Compute-in-Memory (NTHU, UC Santa Barbara)
  • 2.4 HfO2 RRAM Characterization with Various BE Metals (TUBITAK-BILFEM, CEA-LETI)
  • 2.5 RRAM In-Memory Computing of Floating Pt. Multiplication Mapping (Nanyang Tech U.)
  • 2.6 3-stage High Resistance State Retention Behavior in TMO RRAMs (Macronix, NCTU)
  • 2.7 1.4 Mb 40 nm eRRAM Macro with Low Power Read and Hybrid Write Verify(TSMC)
  • 2.8 NVM-Based Deep Learning Acceleration (U. of Texas, San Antonio)
  • 2.9 128Kb eNVM Hybrid HfO2 RRAM (Aix-MarseillesU, IN Lyon, Grenoble Alpes, CEA-LETI)
  • 2.10 2 Mb eRRAM Macro in 65 nm CMOS Logic process (NTHU, TSMC, NCHU)
  • 2.11 ReRAM Single NVM Flip-Flop for NV Processors (NTHU, Tsinghua U, U of C-LA)
  • 2.12 CMOS/RRAM Neural Net with STD Plasticity (Politechico di Milano, IU.NET, Micron)
  • 2.13 Trade-offs in RRAM Characteristics for Various Applications (French Labs, WD)
  • 2.14 True Random Number Generator in 40 nm eRRAM (Panasonic, Kyoto U, Tsukuba U)
  • 2.15 OxRAM for Synaptic Plasticity to Detect Noisy Input Data (CEA, LETI, LIST, INSERM)

3.0 Conductive Bridge RRAM (Cu-RRAM)

  • 3.1 A Low Cost Automotive Grade eCBRAM (Adesto Technology)
  • 3.2 Volatile and Non-Volatile HfO2 CBRAM Switching Characteristics (U. of Notre Dame)
  • 3.3 A Cross-Point Cu RRAM with a BC OTS Selector for Use in SCM Applications (Sony)
  • 3.4 Low Power Cu Atom Switch Programmable Logic Made in 40 nm CMOS ( NEC)
  • 3.5 A 50x20 Crossbar Switch Block with Two-Varistor CAS for Dense FPGA

4.0 Phase Change Memory

  • 4.1 Carbon Doped GST in 40 nm PCM for 128 Mb Test Chip (CAS, SMIC)
  • 4.2 A 40 nm Low Power Logic Compatible PCM Technology (TSMC)
  • 4.3 32B ePCM for Real-Time Data Processing and Automotive Apps (STM, U.of Pavia)
  • 4.4 DRAM/PCM Hybrid Memory Embedded in a MCU (U. Sci. & Tech of China)
  • 4.5 32 KB Embedded PCM for Automotive and Smart Power (STM, U. Pavia)
  • 4.6 Confined PCM with Thin Metallic Liner for High Endurance SCM (IBM, ULVAC, Macronix)
  • 4.7 The Ultimate Scaling Limits of Phase Change Memory

5.0 Ferroelectric Embedded Memories

  • 5.1 Logic Compatible Fe Weight Cell for Gate of HKMG MOSFET (U. Notre Dame, Samsung)
  • 5.2 Hybrid 10nm 1T eDRAM & eNVM Fe-FinFET Using HfZrO Fe(CAS, E. China Normal U).
  • 5.3 nvSRAM Using Ferroelectric HfO2 Capacitor for Ultralow Power IoT (U. of Tokyo)
  • 5.4 Circuit Compatible Compact Model for FeFET (U. of Notre Dame)
  • 5.5 FeFET Nonvolatile Flip-Flops (Tsinghua U., Penn St. U., U. of Notre Dame, Purdue U, NTHU)
  • 5.6 Threshold Switch Augmented Hybrid-FeFET for NVM (U. Notre Dame, Purdue, Virginia)
  • 5.7 Reliability of FRAM PZT Capacitors for HT bake and high field cycling (U. Florida, TI)
  • 5.8 Embedded Ferroelectric HiO2 Capacitor in NV-SRAM (University of Tokyo)
  • 5.9 NV Computing using Negative Capacitance FET (Penn St., Georgia Tech, NTHU, Notre Dame)
  • 5.10 Ferroelectric HfO2 MIM Capacitor NV SRAM for Normally-Off Devices (U. of Tokyo)
  • 5.11 Vertically Stacked Ferroelectric Al:HfO2 FeFETs for NAND use (KU Leven, IMEC)
  • 5.12 Embedded 28 nm Low Power Ferroelectric FET (FeFET) Memory
  • 5.13 Non-Volatile DRAM Using An Anti-Ferroelectric Dielectric

6.0 Magnetic RAM Embedded Memory

  • 6.1 Testing 22 nm FD-SOI eMRAM for Automotive Grade1 Aps (GlobalFoundries)
  • 6.2 Low Damage MTJ Process for 128Mb eSTT-MRAM (Tohoku U, Tokyo Electron, Advantest)
  • 6.3 Low RA MTJ with Low Switching Current for sub-10 nm. (Qualcomm, Applied Materials)
  • 6.4 Process Optimization of pMTJ Arrays for LLC at 7nm and Beyond (Applied Materials)
  • 6.5 eSTT-MRAM in 28 nm FDSOI Logic Process for Industrial Temperature (Samsung)
  • 6.6 pSTT-MRAM Thermal Stability Dependence on Temperature (CEA-LETI, SPINTEC)
  • 6.7 Energy Efficient and Variation Tolerant NVLogic using MRAM (Arizona State U. )
  • 6.8 Overview of pMTJ MRAM for Use in Secure IoT Systems (Qualcomm)
  • 6.9 Spin Orbit Torque pMTJ MRAM with sub 100 ns pulses (Cornell & Purdue Us, Intel)
  • 6.10 Gain-cell MRAM for High Density Storage (U. Rochester)
  • 6.11 STT-MRAM for L2 Cache and Embedded Memory (U. Missouri Kansas City)
  • 6.12 STT-MRAM Cache Design for 3D Multiprocessors (Iran U. of S&T, Ryerson U.)
  • 6.13 NV Data Cache in Mobile Device (Normal Beijing, Shenzhen, Chongqing & Hong Kong Poly)
  • 6.14 embedded STT-MRAM for Automotive
  • 6.15 Low Power Dense pSTT-MRAM for Industrial Systems (IMEC, U. Comp. KU Leuven)
  • 6.16 3T Complementary STT-MRAM Cell with Improved Performance (IMEC, KU Leuven)
  • 6.17 STT-MRAM NV Logic in CMOS/MTJ Hybrid Brain Inspired Circuits (Tohoku U.)
  • 6.18 Obstacles to Embedding MRAM in High Performance CMOS MCU
  • 6.19 Perpendicular Anisotropy in <30 nm MRAM devices for LLC (TDK-Headway)
  • 6.20 Technique to Improve Endurance of STT-MRAM caches in Chip Multiprocessors

7.0 Charge Trapping Embedded Flash Technology and Circuits

  • 7.1 Low Power SONOS eNVM in 40 nm CMOS Logic (Cypress and UMC)
  • 7.2 Graphene Oxide Quantum Dot CT Memory (Hebei U, NUS, S. Illinois U, Purdue U)
  • 7.3 80Kb logic CT MTP Memory with No Process Adders (GlobalFoundries, IIT, UCLA)
  • 7.4 Area effects of TFT Charge Trapping Embedded Memory (Kyung Hee U, ETRI)
  • 7.5 eCharge Trapping Memory in Smart IoT and Automotive applications (Renesas)
  • 7.6 Indium-Oxide Nanoparticle Ox-RRAMs in CMOS BEOL.
  • 7.7 Logic Compatible MTP NVM for High-k-Metal-Gate CMOS Technologies
  • 7.8 Fast FinFET Split-Gate MONOS 16/14 nm eFlash Technology

8.0 Embedded Flash in CMOS Logic

  • 8.1 Embedded Select in Trench Memory for 40 nm MCU Logic (STMicroelectronics)
  • 8.2 STDP and UnSupervised Learning in a NOR Flash Memory Array (Politecnico di Milano)
  • 8.3 28 nm Split Gate SSS embedded flash cell in UMC Technology (Microchip, UMC)
  • 8.4 HTO for Thick Oxide HV Transistors in 40 nm eFlash (STM, Sophia-Antipolis U.)
  • 8.5 40 nm Split-Gate eFlash Cell for Auto Microcontrollers (GlobalFoundries, SST Microchip)
  • 8.6 Method for Improving Endurance of MLC NVM (Waseda U.)
  • 8.7 Construction of Flash Memories Embedded in HKMG Logic Technology
  • 8.8 1Mb NOR eFlash for High Temp. Sensor Nodes (U. of Michigan, TSMC)

9.0 Logic Based Memories

  • 9.1 Logic Compatible multilevel 5T eFlash Memory used in a Neuromorphic core.
  • 9.2 140 MHZ 1Mb 2T1C Gain Cell Using IGZO FETs in CMOS Logic (SEL, UMC, U. Tokyo)

10.0 Organic Embedded NV Memories

  • 10.1 RRAM Polymer with 1D Nanocarbon in a TiO2 layer (Dankook U, Korea U, Korea IST)
  • 10.2 NV Organic Transistor Memory using Quantum Dot Floating Gate (Fuzhou U.)

11.0 Foundries for Embedded Non-volatile Memories

  • 11.1 Global Foundries
    • 11.1.1 Testing 22 nm FD-SOI eMRAM for Automotive Grade1 Aps (GlobalFoundries)
    • 11.1.2 40 nm Split-Gate eFlash Cell for Auto Microcontrollers (GlobalFoundries, SST Microchip)
    • 11.1.3 C Doping Effect on Poly Grain Size in 40 nm eNVM (Singapore UTD, Global Foundries)
    • 11.1.4 80Kb Logic CT MTP Memory with No Process Adders (GlobalFoundries (IIT, UCLA)
    • 11.1.5 FeFET eNVM in 28 nm Single Layer Poly HKMG
  • 11.2 Panasonic Semiconductor
    • 11.2.1 Embedded 512KB ReRAM (Panasonic)
  • 11.3 Samsung
    • 11.3.1 eSTT-MRAM in 28 nm FDSOI Logic Process for Industrial Temperature (Samsung)
  • 11.4 SMIC
    • 11.4.1 Carbon Doped GST in 40 nm PCM for 128 Mb Test Chip (CAS, SMIC)
  • 11.5 STMicroelectronics
    • 11.5.1 Embedded Select in Trench Memory for 40 nm MCU Logic (STMicroelectronics)
    • 11.5.2 ePCM for Read-Time Data Processing and Automotive Apps (STM, U.of Pavia)
    • 11.5.3 32 KB Embedded PCM for Automotive and Smart Power (STM, U. Pavia)
  • 11.6 TSMC
    • 11.6.1 A 40 nm Low Power Logic Compatible PCM Technology (TSMC)
    • 11.6.2 1.4 Mb 40 nm eRRAM Macro with Low Power Read and Hybrid Write Verify(TSMC)
    • 11.6.3 2 Mb eRRAM Macro in 65 nm CMOS Logic process (NTHU, TSMC, NCHU)
    • 11.6.4 Low Power Dense pSTT-MRAM for Industrial Systems (IMEC, U. Comp. KU Leuven)
    • 11.6.5 eFlash for Automotive, Mobile, IoT and Fast Computing (TSMC)
    • 11.6.6 TSMC embedded STT-MRAM for Automotive
    • 11.6.7 Antifuse OTP Macro Using Gate-Oxide Breakdown for Programming (TSMC)
  • 11.7 UMC
    • 11.7.1 Low Power SONOS eNVM in 40 nm CMOS Logic (Cypress and UMC)
    • 11.7.2 28 nm Split Gate SSS embedded flash cell in UMC Technology (Microchip, UMC)

12.0 Embedded NVM Peripheral Circuits

  • 12.1 Dual-Data line read method for fast low energy resistive NVM (UCLA, Inston, NTHU)
  • 12.2 Single Ended Sense Amplifier for Non-Volatile Memories (Starchip, Aix Marceille U.)
  • 12.3 Self-Compensated Sense Amplifier for 130 nm FeRAM (TI)
  • 12.4 Overwrite Purging of Scratch Pad NVM in Embedded Systems (Sharif U of Tech)

Bibliography

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