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3D RRAM Cross-Point Arrays, September 2018
(Applications, Technology, Circuits, Selectors, 3D modeling, Thermal Characterization, Monolithic integration)

This report includes 3D RRAM cross-point array applications, technology, circuits, selectors, 3D modeling, thermal characterization and monolithic integration. Applications include: Storage Class Memory, Big Data Search Applications, Neuromorphic systems, Logic-in-RRAM and FPGAs and RRAM Physical Unclonable Functions (PUFs).

Various 3D RRAMs are reviewed including: Metal Oxide (Anion), Conductive Bridge (Cation) RRAM, non-filamentary (PCMO) RRAM, self-rectifying RRAM (Schottky barrier) and Phase Change Memory. RRAM array device and circuit developments include: timing characteristics, IR drop, methods for improving write latency, access methods, improved sensing, sneak current issues, 3D array organizations and temperature compensation. 3D RRAM process architectures included: horizontal, stacked multilayer arrays, BiCs VRRAM, VRRAM on FinFET and self-aligned VRRAM. Self-selecting, selectorless and reduced selector cross-point arrays.

Reliability of RRAM arrays include techniques to: improve endurance, minimize energy, provide sufficient margin, reduce disturb failure and improve transient control during fast operation. Thermal characteristics of 3D RRAM arrays include: effect of thermal resistance, scaling, thermal analysis of thin film arrays, electrothermal characterization, disturbance due to thermal crosstalk and transient thermal disturbance.. Modeling and characterization of various 3D RRAM arrays is described.

Selectors for RRAM Cross-bar arrays were reviewed including: CuSiOx and Ag/SiOx drivers, MoS2 drivers, HfO2 bilayer selector, integrated OTS selectors, BC doped OTS selectors, Threshold switching IMT devices (V &Nb), MIEC access devices, metal dichalcogenide selectors, Ag filament threshold switching devices and doped SiO2 film selectors. Complementary resistive switching (CRS) RRAMs were reviewed. Monolithic 3D RRAM high density array integration using 50 nm monolithic inter-tier vias (MIV) on sequential single substrates is covered along with advances in conventional 3D RRAM system stacks using TSVs.

180+ pages.

3D RRAM Cross-Point Arrays, September 2018
(Applications, Technology, Circuits, Selectors, 3D modeling, Thermal Characterization, Monolithic integration)

Table of Contents

Executive Summary

1.0 Overview and Applications

• 1.1 Overview of 3D Cross-Point Array Memory Applications
• 1.2 Storage Class Memory
  • 1.2.1 Overview of Storage Class Memory Applications
  • 1.2.2 Cross-Point 1S1R Cu- ReRAM with BC doped OTS Selector for Storage Class Memory
  • 1.2.3 Heterogenous Storage Class Memory for Improved Performance and Reduced Cost.
  • 1.2.4 Cross-Point Cu-RRAM and Boron+Carbon OTS Switch for SCM Applications
  • 1.2.5 Considerations of High Density PCM for Use in Storage Class Memory
  • 1.2.6 Power Management for High Density 3D Cross-Point Arrays for Mobile Devices
  • 1.2.7 Evolution of Storage Class Memory
  • 1.2.8 Categorizing of MLC Storage Class Memory Using Two Types of RRAM
• 1.3 RRAMs in Big Data Search Applications (TCAMs,)
  • 1.3.1 `Non-Volatile Ternary CAM (TCAM) with Two HfO2/Al2O3/GeOx/Ge MOS diodes
  • 1.3.2 RRAM Boost Converter for RRAM and NAND Hybrid SSD Clouds Storage
  • 1.3.3 Circuit Level Simulator for Emerging NVM based TCAMs
  • 1.3.4 256bit Wordlength 2.5T1R ReRAM TCAM in CMOS Logic
• 1.4 RRAMs in Neuromorphic and Other Computing Systems
  • 1.4.1 Overview of Neuromorphic Systems
  • 1.4.2 Direct RRAM Cross-Point Array Matrix Multiplication without A/D Conversion
  • 1.4.3 Methodology to Improve Linearity of Analog RRAM for Neuromorphic Computing
  • 1.4.4 TaOx RRAM TSV System for Real-Time Image Recognition of IoT Edge Devices
  • 1.4.5 4M Synapses Integrated Analog RRAM for Use in a Low Power Neural Network Processor.
  • 1.4.6 In-Memory Computation using a Neural Network with a 1T1R RRAM Array
  • 1.4.7 Hyperdimensional Computing Using CN-FETs and RRAM
  • 1.4.8 Processing-in-Storage Accelerator for Machine Learning
  • 1.4.9. PCMO RRAM as Analog Neuromorphic Synapse
  • 1.4.10 Mapping a Tensorized Neural Network onto a 3D CMOS RRAM
  • 1.4.11 1T2R Synapse Device for Neuromorphic Systems
  • 1.4.12 V-RRAM-based 3D Neuromorphic System for Associative Memory Learning
  • 1.4.13 Ternary Neural Network using 3D Vertical RRAM Array
  • 1.4.14 Computation of Boolean Matrix Chain Products in 3D RRAM
  • 1.4.15 Hyperdimensional Computing using 3D VRRAM In-Memory Kernels
  • 1.4.16 3D Multi-layer CMOS RRAM Accelerator for a Neural Network
  • 1.4.17 Metal/PCMO RRAM Analog Synapse and IMT Neuron for Neuromorphic System
  • 1.4.18 A Compact Oscillation Neuron Cell Using a 2T+1R Resistive Synaptic Array
  • 1.4.19 HfO2 RRAMs as Synapses for Convolutional Neural Networks
• 1.5 RRAM in Logic and FPGAs
  • 1.5.1 Overview of RRAM in Logic
  • 1.5.2 Fine Grained 3D Reconfigurable Computing Fabric for FPGA with RRAM
  • 1.5.3 A Cross-bar Memristive Logic-in-Memory RRAM-based Architecture
  • 1.5.4 Review of CMOS Compatible Embedded Emerging Memories
  • 1.5.5 Normally-off Logic Using Resistive Switches for Instant-On Circuits
  • 1.5.6 Low Power FPGA Using Integrated RRAMs
• 1.6 Circuits Using Embedded ReRAM
  • 1.6.1 Overview of Logic Circuits with Embedded ReRAM
  • 1.6.2 nvMCU with 65 nm eReRAM for NV Processing
  • 1.6.3 Multistate Register Using RRAM
  • 1.6.4 Single RRAM nvSRAM for Reduced Store/Restore Energy
• 1.7 RRAM for Physical Unclonable Function (PUF) and Random Number Generators
  • 1.7.1 Overview of ReRAM Physical Unclonable Function (PUF)
  • 1.7.2 Using an Analog RRAM crosspoint Array for a PUF
  • 1.7.3 Using Sneak Path Current in a RRAM Cross-point Array to Make a Strong PUF.
  • 1.7.4 Quality PUF Extraction from Commercial RRAM using Switching Time Variability
  • 1.7.5 True Random Number Generator (RNG) based on an RRAM PUF
  • 1.7.6 RRAM-based PUF for Hardware Security
  • 1.7.7 Random Number Generator Based on RRAM
• 1.8 RRAMs for Space Applications
  • 1.8.1 Low Temp Switching of Pt/HfOx/TiN RRAM for Aerospace

2.0 RRAM Chips - Device and Circuitry

• 2.1 Overview of ReRAM Device and Circuits
• 2.2 Improving Timing Characteristics of 3D RRAM Arrays
  • 2.2.1 A Changing Reference Parasitic Matching Sensing Circuit for 3D VRRAM
  • 2.2.2 Using Cross-bar Characteristics to Improve Write Latency for 3D RRAM Arrays
  • 2.2.3 Sense Amp and Write Termination Method for eRRAM Macro
• 2.4 Improving Energy Consumption of RRAM Array
  • 2.4.1 Multilayer Approach for Design of Energy Efficient, Reliable RRAM CPA System
• 2.5 Design Considerations for 3D RRAM Cross-bar Arrays
  • 2.5.1 Design of Terabit Dense 3D Vertical RRAM with Required Selector Characteristics
  • 2.5.2 A Differential 3R-2bit CP RRAM Array to Reduce Power & Improve Read Margin
  • 2.5.3 Sneak Current Cancellation Scheme for 3D Vertical RRAM Crossbar Array
  • 2.5.4 Design Considerations for VRRAM 3D Cross-Point Arrays
  • 2.5.5 Integrated 3D Cross-Point RRAM with New Write Driver and Sense Amplifier
  • 2.5.6 Sensing Circuit Improves Sense Margin in Scaled RRAM

3.0 ReRAM Cell and 3D Chip and Array Process and Architecture

• 3.1 Overview of Cross-Point Array Process Architecture
• 3.2 A BiCs Structure TaOx-Type 3D Vertical RRAM Array
• 3.3 Three State MLC HfOx RRAM in 16Kbit cross-point cell array
• 3.4 Modeling and Fabrication of a 3D synaptic Array using VRRAM
• 3.5 Self-Select 28/20nm RRAM Cell in HKMG CMOS with sub-uA Switching current
• 3.6 4-Layer Vertical RRAM Integrated with FinFET
• 3.7 3D Vertical RRAM with Self Aligned Self Selective Cell in sub 5nm Technology
• 3.8 Implementation of Bilayer 3D RRAM Cross-bar Array
• 3.9 Surface Roughness on ZnO ReRAM
• 3.10 A Low Cost Manufacturable 16 nm FINFET RRAM Logic Process
• 3.11 3D Vertical Structure for 1TnR Non-linear RRAM

4.0 Selectorless and Reduced Selector (1TnR) Cross-Point Memory Arrays

• 4.1 Overview of Selectorless and Reduced Selector Cross-Point Memory Arrays
• 4.2 Reducing Sneak Current in RRAM Cross-Bar Arrays
  • 4.2.1 Reducing Sneak Current with a 1 Step Row Readout in Selector-Less Array
  • 4.2.2 Read Accuracy in Linear, Selectorless Arrays using Various Read Methods
  • 4.2.3 Architecture Using Horizontal 3D RRAM for Depressing Sneak Current
  • 4.2.4 Reducing Sneak Current in RRAM Cross-bars by Distributing Insulating Nodes
• 4.3 1TnR Cross-Point Vertical RRAM Arrays
  • 4.3.1 Overview of 1TnR Vertical RRAM Arrays
  • 4.3.2 Sneak-Path based Test for 3D Stacked 1T+NRRAM array
  • 4.3.3. 1TnR Array Architecture Using Carbon Nanotube FET Selector.
• 4.4 Reducing Sneak Current in 0TNR Self-Rectifying Cross-Point Arrays
  • 4.4.1 New Charge-Pump Read Method for Nonlinear sub-Teraohm 0TNR VRRAM

5.0 Bipolar Oxide RRAM Devices / Anion RRAM Devices and their Characteristics

• 5.1 Self-Rectifying Oxide RRAM
  • 5.1.1. Self Rectifying and Forming-Free RRAM for High Density CMOS Compatible VRRAM
  • 5.1.2 Switching Mechanism of Self-Selective Cell in 3D VRRAM Oxide RRAM
• 5.2 3D RRAM Oxide Devices Using BiLayer Design
  • 5.2.1 3D RRAM Devices Made using TiOx/Al2O3 bilayer design.
  • 5.2.2 MLC HRS Control in TiN/HfOx/Pt Oxide RRAM
• 5.3 One Selector One RRAM (1S1R) Oxide RRAM Devices
  • 5.3.1 Finding an Optimal ON/OFF Resistance Ratio for A 1D1R RRAM
  • 5.3.2 Vertical Thin Film 1S1R RRAM/Selector for Oxide RRAM High Density Arrays
• 5.4 Various Oxide ReRAM Devices / Anion RRAM Device Studies
  • 5.4.1 Analysis of Cerium Oxide Bipolar ReRAM
  • 5.4.2 ITO RRAM Stop Voltage & I Compliance
  • 5.4.3 Triple Ion Effect in GeSO RRAM

6.0 Non-Filamentary (PCMO) RRAMs

• 6.1 Enhanced Memory by Ion Transport Barrier Tuning for PCMO Selectorless RRAM
• 6.2 Selectorless Non-Linear PCMO RRAM
• 6.3 Self-Heating during sub-us Current Transients in PCMO-Based RRAM
• 6.4 PCMO Selector, RRAM and Self-Selecting Selectorless RRAM
• 6.5 Variability and Its Improvement in PCMO-based RRAM
• 6.6 Ti/WO3/ZrO2/W RRAMs for Non-Filamentary Homogeneous Switching

7.0 3-D Phase Change Memory Arrays

• 7.1 High Endurance Self-Heating OTS-PCM Pillar Cell for 3D Stackable Memory
• 7.2 Stacked PCM + OTS with High Sub-Threshold Non-Linearity for NonSwitching Read
• 7.3 Multi-domain Compact Model for GeSbTe Phase Change Memory and Selectors
• 7.4 Progress in PCM Technology
• 7.5 Impact of SiN Resistive Heater & W Bottom Contact of Read Reliability of PCM Cell
• 7.6 Power Supply Systems in 3-D ICs Using Phase Change Memory

8.0 Characteristics of Conductive Bridge (Cation) ReRAM

• 8.1 Overview of Conductive Bridge RAM Characteristics
• 8.2 Cross-Point 1S1R Cation-Type Cu- ReRAM with BC doped OTS Selector for SCM
• 8.3 Cross-Point Cu-RRAM and Boron+Carbon based OTS Switch
• 8.4 Device Simulation and Modeling of the Switching Process in CB-RAMS
• 8.5 Single Event Susceptibility in CB-RAM
• 8.6 Method for Tightening Vset and Vreset Distributions of CB-RAM
• 8.7 Operating Current Dependence of Cu Mobility in CB-RAM

9.0 Reliability of High Density RRAM

• 9.1 Improving Endurance in HfO2/Ti Metal Oxide RRAM 1T1r K-bit Arrays
• 9.2 Random Telegraph Signal Noise (RTS) in Advanced RRAMs
• 9.3 Cycling Induced Trap Creation and SET Disturb in 3D RRAM Memories
• 9.4 Transient Control of RRAM for High Speed and High Endurance
• 9.5 RRAM Refresh Circuit to resolve soft error Failures in HrO2/Hf 1T1R RRAM Cells
• 9.6 Pulse Program to Suppress Retention Tails in OX-RRAMS
• 9.7 Resistance Instability in HfO2 RRAM
• 9.8 Cycling Degradation of HfOx ReRAM
• 9.9 Program-Verify Algorithm for Multi-bit HfO2 RRAM Operation
• 9.10 Tailing of Resistive State Distributions in HfOx and TaOx RRAM
• 9.11 HfO2 RRAM Forming/Switch Variability
• 9.12 Endurance Failure Model for Filamentary HfO2 RRAM
• 9.13 Test Considerations for New Memory Technologies

10.0 Thermal Characteristics in 3D RRAM Arrays

• 10.1 Thermal Optimization of 2.5D and 3D Stacked RRAM
• 10.2 Effect of Thermal Resistance and Scaling on PCMO-based RRAMs
• 10.3 Thermal Analysis of Thin-Film Stacked Cross-bar RRAM Integrated in 3D ICs
• 10.4 Electrothermal Characterization of 3D RRAM Arrays
• 10.5 Microsecond Transient Thermal Disturb During Operation of HfOx-based RRAM
• 10.6 Atom Level Electro-Thermal Model of Bipolar TiO2 RRAM
• 10.7 Simulation and Thermal Characteristics in Silicon Rich RRAMs in 3D Arrays
• 10.8 Thermomic Measurements on Filamentary RRAM

11.0 Modeling and Characterization of f 3D RRAM Arrays

• 11.1 Model of Multifilamentary Conduction for High Density TMO-RRAM
• 11.2 A Quasi-Analytical Model of the 3D VRRAM Array for MB-Level Design
• 11.3 Design and Modeling of Cross-point and VRRAM arrays using 1S1R Cells
• 11.4 Model for 3D RRAM Arrays including Thermal Effect
• 11.5 Stochastic Differential Equation & Percolation Hopping Model for RRAM
• 11.6 Compact Model of Bipolar RRAM Cells

12.0 Selector Drivers for Bipolar RRAM Cross-Bar Arrays

• 12.1 Overview of Selector/Drivers for Cross-Bar Arrays
• 12.2 Metal Oxide Selectors for RRAM Cross-Bar Arrays
  • 12.2.1 Resistive Switching of Cu/SiOx&Ag/SiOx Conductive Bridge RAM Select Device
  • 12.2.2 Monolithic Integration of MoS2 Transistor for Driving RRAM in 1T1R Array
  • 12.2.3 Cu BEOL Compatible HfO2 Diode Selector with Ultra Low off-current
  • 12.2.4 1S1R ReRAM Using NbO2 Selector in 4F2 2x nm Technology
• 12.3 OTS/Chalcogenide Selectors (See also PCM Devices)
  • 12.3.1 Integrated OTS Selector with Low leakage at Vth/2 Bias Down to 1 ns Range
  • 12.3.2 Te-based Binary OTS Selectors with Good Characteristics
  • 12.3.3 BC doped OTS Selector for use with 1S1R Cross-point Cu-ReRAM
  • 12.3.4 Boron+Carbon based OTS Switch for Cross-Point Cu-RRAM
• 12.4 Threshold Switching IMT Select Devices using V or Nb
  • 12.4.1 Cr-doped Amorphous Vanadium Oxide for 3D RRAM Array Selectors
• 12.5 MIEC Access Devices for 3D Cross Bar Arrays
  • 12.5.1 Using MIEC access Devices for 3D Cross-bar Arrays Larger than 1 Mbit
• 12.6 Metal Dichalcogenide Selectors for Vertical RRAMs
  • 12.6.1 2-Terminal Vertical Transition Metal Dichalcogenide Selectors for RRAMs
• 12.7 Ag Filament Threshold Switching Devices
  • 12.7.1 Ag filament Threshold Switching Selector After Rapid Thermal Processing
  • 12.7.2 Effect of Liner Thickness on AgTe/TiO2 Threshold Switching Devices
• 12.8 As Doped SiO2 Selectors for RRAM Arrays
  • 12.8.1 As Doped SiO2 Film Based Selector for 1S1R RRAM Cell Array

13.0 Complementary Resistive Switching in RRAM Cross-Point Arrays

• 13.1 Overview of Complementary Switching ReRAMs
• 13.2 Modeling Redox-based RRAMs and Predicting CRS Switching
• 13.3 3-bit RRAM Write-Read Method based on a Complementary Switching Mechanism
• 13.4 HfOx CRS Switches Using a Nanodamascene Process
• 13.5 Power Selector-less Crossbar Array with Complementary Resistive Switching
• 13.6 3D Bilayer SCC 1S1R HfOx/MIEC Cell

14.0 3D Integration of Stacked RRAMs

• 14.1 Overview of 3D RRAM Crossbar Arrays and Systems
• 14.2 Monolithic 3D RRAM Array Integration Using MIV
  • 14.2.1 Energy Efficient Monolithic 3D On-Chip Memory Architectures
  • 14.2.2 High Dimensional Computing Characteristics and use of High Density RRAM
  • 14.2.3 Energy Efficient Monolithic 3D Memory Architectures
  • 14.2.4 Fabrication and Characterization of Monolithic 3D RRAM Crossbar Arrays
  • 14.2.5 Monolithic Epi-like Silicon Thin-Body Multichannel Integrated 3D IoT Chip
  • 14.2.6 3D Stacked Monolithic IC using ILVs connecting RRAM and CNT Layers
• 14.3 3D RRAM Stacks using TSVs
  • 14.3.1 3D ReRAM and NAND Flash SSD with 0.6V Boost Converter and Charge Pump
  • 14.3.2 Removing IC Stack Heat with Percolating Thermal Underfill with NP Necks

Bibliography

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