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Security Issues for Processors with Memory, June 2018

(Embedded Key Storage, memory PUFs, security in image processing, external attacks on IoT Chips with eMemory,
hardware and software Trojans, secure mobile and main memory subsystems, volatile memory attacks.
Tracking secure chips, Security on IoT devices using energy harvesting and Security against side channel attacks)

With nearly all electronic systems interconnected today, chip security has become one of the pressing IC issues. Chip security issues frequently involve memory since data entering or leaving the chip is most likely to be what is compromised. A memory chip can be used for embedded key storage to resist attacks. This key can be a physical unclonable function (PUF) made as a unique IC identifier derived from unique process variations in the embedded memory in the IC. Security issues for IoT have become critical with attacks occurring throughout the network and in SoC processor chips and FPGAs with embedded memory. Many protective techniques have been described including, firewalls, encryption, and resource isolation. Hardware Trojans (malicious modifications of IC hardware) have been described. Software Trojans involving modifications of software particularly IDing and extracting memory contents in the bit stream have been discussed. Mobile system security has been improved using, for example, RRAM as flexible memory. Issues of volatile vs. non-volatile memory for cache and main memory involve consideration of security hazards. Cryptography in multicore coprocessor systems are an issue. Security of data on network buses is critical for military, medical and financial systems with remedies suggested for replay attacks. Environmental attacks on memories can be used to tamper with stored data. IC/memory counterfeiting is a security issue that can be remedied in part by using aging effect monitors. PUFs can also be used to record age. Intermediate states can be stored in energy harvesting devices and potentially encrypted. Side channel attacks target particularly the current and timing asymmetries in many memory devices and several remedies have been suggested.

90+ pages.

Security Issues for Processors with Memory, June 2018

Table of Contents

1. Introduction to Chip Security Issues Involving Memory

2.0 Embedded Key Storage in Memory arrays and FPGAs

• 2.1 Overview of Embedded Key Storage in Memory
• 2.2 RRAM Memory chip for embedded key storage with physical security
• 2.3 Threshold-based Keys and ECC for Security against Invasive Readout
• 2.4 Hardware Security Module for Non-volatile FPGAs for Private Key Managment

3.0 Physically Unclonable Functions for Secure Key Generation

• 3.1 Overview of Physically Unclonable Functions for Secure Key Storage
• 3.2 Secure Key Generation Using Physically Unclonable Functions
• 3.3 SRAM-Based PUFs for Unique Chip Identifiers
• 3.4 Using Resistive RAM as a PUF for Hardware Security Primitive
• 3.5 Circuit Design Considerations for PUFs for Security Applications
• 3.6 Reconfigurable Tristate SRAM PUF
• 3.7 Reconfigurable DRAM-based PUF
• 3.8 An RRAM Based PUF with Differential Read-Out Method
• 3.9 DRAM-Based PUF for Security and Authentication
• 3.10 Forming a Stable Non-Volatile Reproducible PUF from CMOS Breakdown Position.
• 3.11 Comparison of 28nm planar vs. 16 nm FinFET SRAM PUF
• 3.12 Strong RRAM PUF
• 3.13 Experimental Reduction of SRAM PUF BER using 180nm 256-bit SRAM PUFs
• 3.14 Nonvolatile PUF using STT MRAM
• 3.15 Using an SRAM as an analog PUF
• 3.16 Using a 8T-Dual Port_ SRAM to Create a PUF
• 3.17 The Potential for Using DDR DRAM Start-up bits As a True RNG
• 3.18 Effect of Power Supply Ramp Time on SRAM PUF’s
• 3.19 Double-layer array RRAM PUF for use against Machine Learning Attacks
• 3.20 Register-based PUF with No Power-up Restrictions

4.0 Security in Image Processing and Face Detection

• 4.1. Overview of Image Processing in Security Applications
• 4.2 High Resolution CMOS Image Sensor for Security Applications[
• 4.3 Using CPU-FPGA Acceleration for Face Detection

5.0 Attacks on Processor Chips with Embedded Memory

• 5.1 Overview of Attacks on IoT Processor Chips with Embedded Memory
• 5.2 Multi-Processor IoT SoC Attacks
• 5.3 Cache-Assisted Secure Execution on ARM Processors
• 5.4 Method for System Level Security for Heterogeneous MPSoCs
• 5.5 Securing the Design-for-Test Circuitry on an SoC
• 5.6 Using Secure Zones to Prevent Attacks in NoC-based MPSoc
• 5.7 Using Embedded Memories in Secure Applications
• 5.8 A Single Protection Measure against Attack of AES Protected Low Power IoT Devices
• 5.9 Encryption and Authentication against Run-Time Attacks on SRAM in FPGAs
• 5.10 A Trusted Virtual Sensor CMOS Design
• 5.11 Cache Behavior of in-Memory Tag Tables Using Merged Cache Hierarchy for DRAM
• 5.12 Reconfigurable Low Power DTLS Cryptographic Engine for IoT-to-Cloud Security
• 5.13 Conditions for Securing IoT to Cloud Systems using a Computational Fuzzy Extractor

6.0 Hardware Attacks on IC Chips

• 6.1 Overview of Hardware Trojans
• 6.2 Hardware Trojan Prevention and Detection in IC Chips
• 6.3 Trojans Modifying Soft-Processor Instructions Embedded in FPGA Bitstreams

7.0 Software Trojans - Malicious Modifications of Bitstreams

• 7.1 Overview of Software Trojans
• 7.2 Trojans Modifying Soft-Processor Instructions Embedded in FPGA Bitstreams
• 7.3 Secure Boot for Linux-based embedded systems on FPGAs

8.0 Increasing Effective Memory in Mobile Systems

• 8.1 Overview of Secure Memory in Mobile Systems
• 8.2 Morphable Resistive Memory in Mobile systems
• 8.3. Vocoders in Mobile Devices for Military Applications

9.0 Secure Main Memory Subsystems

• 9.1 Overview of Secure Main Memory Subsystems
• 9.2 High Performance STT-RAM Main Memory Subsystem
• 9.3 ECC in Space Memory to Compensate for Radiation Induced Errors.
• 9.4 Cryptographic Assists for the AES of a 14 nm MPU for a Next Generation Mainframe

10.0 Security of Networks and Network Buses

• 10.1 Overview of Security of Networks and Network Buses
• 10.2 Hardware Anti-replay Protection in Tb/s Network Accelerator Data Lines
• 10.3 On-Chip Cryptographic units for Security in Wireless IoT Sensor Networks

11.0 Threats to Embedded Persistent Memory

• 11.1 Environmental Security Issues in Spintronic Building Blocks

12.0 Attacks on Volatile Memories, SRAMs and DRAMs

• 12.1 Attacks on Volatile Memories

13.0 Tracking Secure Chip Usage and Authenticity

• 13.1 Overview of Tracking Secure Chip Usage and Authenticity
• 13.2 Using Aging Effects to Track Chip Usage
• 13.3 Detecting Counterfeit IC’s Using On-Chip Sensor and Authentication
• 13.4 Detecting Counterfeit Recycled IC’s by Testing SRAMs for Aging

14.0 Security on IoT Devices using Energy Harvesting

• 14.1 Optimizing Checkpointing for Secure Intermittently-Powered IoT Devices

15.0 Security against Side-Channel Attacks

• 15.1 Overview of Security against Side-Channel Attacks
• 15.2 Higher-Order Masking as a Countermeasure Against Side-Channel Attacks
• 15.3 Evaluation and Protection Against a Side Channel Attack on a NoC based MPSoC

Bibliography

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