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3-D DRAM Stacked TSV System Chips, October 2014
(Design, Architecture, Technology, Modeling, Performance, Test, Yield, Reliability, Stress, Power/Energy, Noise, Variation, 3D Configuration)

This report covers various aspects of TSV connected DRAM-processor system chips. Design and architecture studies include new refresh control methods and cache configurations. Production technology concerns center on issues with thinning the DRAM chips for stacking without warpage and stress and on TSV proximity effects. Various new modeling tools included a thermal simulation tool and a power model. Performance was improved by a redesigned DRAM controller and a logic-in-memory accelerator. Test methods for a DDR4 SDRAM with TSV was discussed, along with partitioning styles for a 3D stacked DDR3 SDRAM. Test of 3D WideIO DRAMs with TSV showed high bandwidth and low power compared to a LPDDR3 configuration. Test challenges for 3D WideIO DRAMs were discussed. A High Bandwidth Memory (HBM) using 4 core DRAMS and a base logic chip was described. Wafer level test of 3D stacked eDRAM was confirmed. 3D repair using spare 2D redundancy was examined. Mechanical stress mechanisms and guidelines were investigated. The effect of thinning the DRAM wafer on the Young's Modulus was discussed along with gettering treatments to prevent Cu diffusion through the wafer backside and from Cu TSV. Various aspects of power management of stacked TSV chips were discussed. Both microfluidic cooling and air cooling in 3D IC systems were considered. The use of temperature sensors was described and the potential was discussed for using a thread migration algorithm in the processor to reduce internal temperature in a 3D stack. TSV coupling noise was reduced by using a guardring, and a global clock distribution technique was suggested. Process reliability concerns centered on Cu contamination both through the back of a thinned DRAM wafer and from Cu TSV with insufficient barrier layer protection. Layer to layer variation in speed for stacked systems was modeled and compensation methods discussed. A Pulse Amplitude Modulation memory I/O interface was proposed to improve energy efficiency in 3D stacked DRAM. An inductive coupling interface was suggested to replace physical TSV connections in 3D memory-processor stacks.

80+ pages.

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Table of Contents

1.0 Overview of TSV DRAM/Memory Systems

2.0 Architecture and Design of TSV DRAM/Processor Chips

• 2.1 Overview of Architecture and Design
• 2.2 Refresh Control Method for 3D Stacked DRAM (Inst. of Comp. Tech, Beijing)
• 2.3 3D Heterogeneous MCP with Stacked L2 DRAM Cache (N. Carolina State U.)
• 2.3.1 3D Heterogeneous MCP (N. Carolina State U.)
• 2.3.2 High Performance L2 Cache Using 3DIC Stacked DRAM (N. Carolina State U)
• 2.4 A New DRAM Interface, the SCDRAM, Using TSV (NTHU, ITRI)
• 2.5 3D TSV integrated DRAM/ReRAM/MLC NAND SSD (U. of Tokyo)
• 2.6 3D TSV Hybrid Memory Cube with New DRAM Architecture (Micron)

3.0 Technology of TSV DRAM/Processor Chips

• 3.1 Overview of Technology of TSV DRAM/Processor Chips
• 3.2 3D Stacking Process for Various Heterogeneous Chips (Chipworks)
• 3.3 Double-Sided Flip-Chip Assembly of 3D Stacked Memory and Controller (Georgia IT)
• 3.4 Challenges in 3D Memory Manufacturing and Process Integration (Micron)
• 3.5 High Performance TSV Interconnects for 3D-IC Using Air Gaps (TSMC)
• 3.6 3DIC with 28 nm Logic and Wide I/O DRAM Using Non-Conductive Film (Renesas)
• 3.7 Stacked Cu - TSV/uBump Chip-on-wafer-on-Substrate Technology (TSMC)
• 3.8 A DLL-Based Data Self-Aligner for Use in TSV Interface (Hynix, Korea U.)
• 3.9 3D Integration with TSV and High-K/Metal Gate CMOS (TSMC)
• 3.10 TSV With Deep Trench Capacitor (IBM)
• 3.11 Chip-to-Wafer Hybrid Self-Assembly with Temporary ES Bonding (NICHe,Tohoku U.)

4.0 Modeling, Simulation and Design for 3D TSV DRAM/Processor Chips

• 4.1 Overview of Modeling, Simulation and Design for 3D TSV DRAM System Chips
• 4.2 Model for 3D DRAM Array Custom Assembly (NTHU, ITRI, Qualcomm, Yuan Ze U, Intel, Fujitsu)
• 4.3 3D Stacked Memory System Architecture with ESL Virtual Platform (ITRI)
• 4.4 Thermal-aware task allocation tool for 3D DRAM-Multicore Stack (Chung Yuan Christian U)
• 4.5 System Power Modeling of 3D Stacked Wide I/O DRAMs (TU Delft)
• 4.6 Design of 3D DRAM/Multi-Core Computing System (Xi'an Jiatong U.)

5.0 Performance in 3D Stacked TSV DRAM Systems

• 5.1 Overview of Performance in 3D Stacked TSV DRAM Systems
• 5.2 Analysis of Wide I/O DRAM Latency Reduction in 3D Systems (U. of Wisconsin)
• 5.3 3D TSV Stacked DRAMs with Logic-in-Memory Accelerator (Carnegie Mellon U.)
• 5.4 High Bandwidth Wide I/O Mobile 3D DRAM Systems Using TSV (Samsung)
• 5.5 Latency and Power Reduction Model for TSV Systems (U. Wisconsin, W. Virginia U., Samsung)

6.0 Test, Yield and Repair of 3D TSV DRAM/Processor Chips

• 6.1 Overview of Test, Yield and Repair of 3D TSV DRAM/Processor Chips
• 6.2 Using a Test Die to Test Passive Interposers at Wafer Sort (Xilinx)
• 6.3 Timing and Test Techniques for 2.4 Gb/s/pin HCM DDR4 SDRAM with TSV(Samsung)
• 6.4 3D DRAM Die Partitioning Effect on Reliability & Yield (Georgia IT, Samsung)
• 6.5 Test and Packaging of 3D DRAM -Logic Chip (Renesas)
• 6.6 128GB/s 8-channel WideIO TSV Stacked DRAM Test Methods (SK Hynix)
• 6.7 3D Wafer Stacking and Test Using Cu TSV for 45 nm eDRAM Technology (IBM)
• 6.8 Reactivation of Spares for Off-Chip Repair after TSV 3D IC Die Stacking (ITRI)
• 6.9 Test Issues for 3D TSV ICs for Chip on Wafer on Substrate (TSMC)
• 6.10 3D IC-DRAM GPS RF System with System BIST (TSMC)
• 6.11 Test of a 3D NoC MP SoC Using Wide IO (CEA, LETI, Minatec, ST-Ericsson, STMicroelectronics
• 6.12 BISR Scheme for 3D RAMS Using Interdie Redundancy (TSMC, Nat.Central U.)
• 6.13 Allocation of RAM BISR Circuits for SOC in 3D ICs (Nat. Central U.)
• 6.14 Repair of 3D TSV-based RAM using BIST and BISR/BIRA (Nat. Taiwan U. of S&T)

7.0 Mechanical Stress Issues in TSV CMOS

• 7.1 overview of Mechanical Stress Issues in TSV CMOS
• 7.2 Underfill-uBump Interaction Mechanism in 3D ICs (IMEC)
• 7.3 Retention of Thinned DRAM Chips in 3D Integration (NICHe, Tohoku U.)
• 7.4 Integration Effect on Retention in a Thinned DRAM Chip for 3DIC (Niche TohokuU)
• 7.5 Degradation of DRAM Retention in Thinned DRAM Chips (Tohoku U., ASAET)
• 7.6 TSV Induced Mechanical Stress of FD Bulk FinFET Technology(IMEC, KU Leuven)
• 7.7 Reducing 3D-LSI Local Deform from Cu-TSV& CuSn/InAu uB (NCHe, ASET, Tohoku U)
• 7.8 Impact of Isolated and Arrayed Via Middle Cu TSV in 28 nm CMOS (TI)

8.0 Power/Energy and Thermal Issues in 3D Logic/Memory TSV and Microbump Stacks

• 8.1 Overview of Power/Energy and Thermal Issues
• 8.2 Power Management of Off-Chip Links for HMC (Seoul Nat. Univ.)
• 8.3 Thermal Behavior for 3D DRAM TSV Stacks (Hanyang U.)
• 8.4 Micro-Fluidic Cooling in 3D ICs (U. of Maryland)
• 8.5 Air-Cooling of 3D TSV Stacked Memory and Processor Die (Hewlett Packard)
• 8.6 3D Temperature Variations vs. Refresh Period in 3D DRAM Stacks (U. of Bologna)
• 8.7 Thermal Effects in a WideIO DRAM/Logic Assembly (U. of Bologna)
• 8.8 3DIC System Increase in Energy Efficiency from Microfluidic Cooling (U. of Maryland)
• 8.9 Thermal and Supply Crosstalk of 3-D Integrated SRAM (Georgia Tech)
• 8.10 Energy Efficiency for 3-D TSV DRAM Systems (U.of Kaiserslautern& Bologna)
• 8.11 Thermal reduction in 3D Stack Using Thread Migration (U. Calif. Irvine, George Mason U.)
• 8.12 Stacking of SRAM Cache & 3-D DRAM to Reduce Dynamic Energy(Intel, Georgia IT)
• 8.13 Power Delivery Networks in 3D IC (Stanford, Monolithic 3D, Rambus)
• 8.14 Analytical Simulations to Analyze Various TSV-based 3D PDNs (Rensselaer)

9.0 Noise, Decoupling and Clock Distribution Considerations with TSV.

• 9.1 Overview of Noise, Decoupling and Clock Distribution with TSV
• 9.2 Guard Ring Technique to Reduce Coupling Noise in TSV (SK Hynix, Seoul Nat. U.)
• 9.3 Minimizing Noise in a Neural Microsystem Using TSV (NCTU, China M.U., ASEG)
• 9.4 Shorted Global Clock Distribution for 3D TSV Stacked eDRAM Chips (IBM)

10.0 Process Reliability Issues in 3D DRAM Integration

• 10.1 Overview of Process Reliability Issues in 3D DRAM
• 10.2 Thinning a 300 mm DRAM Wafer to 4 um (TokyoIT, Disco, Fujitsu, Dai Nippon Pringing, PEZY)
• 10.3 Reliability Effects of Cu Contamination in Thinned 3D DRAM (NICHe, Tohoku Univ.)
• 10.4 Impact of Cu Contamination on Backside of Thinned Wafer (NICHe and Tohoku U.)
• 10.5 Process for Via-Middle TSV Process for DRAMs (SK Hynix)
• 10.6 Process Reliability Issues of 3D LSI in SiP with TSV (NICHe, Tohoku U.)
• 10.7 Silicon Lattice Quality in 3D LSI with TSV and uBumps (NICHe)

11.0 Variation Considerations in Using TSV With Memory

• 11.1 Overview of Variation Considerations in TSV Memory
• 11.2 Improving 3DIC Cache Performance Through Management of Variation (U. of Pittsburgh)
• 11.3 Process Variation Aware 3D DRAM-to-Core Cache Management (U. of Pittsburgh)

12.0 Research into 3D TSV Stacking

• 12.1 Overview of Research into 3D TSV Stacking
• 12.2 Vertical Graphene Contacts for Thermal Carbon TSV (AIST)

13.0 Configuring Stacked TSV Memory Systems

• 13.1 Overview of Configuring Stacked TSV Memory Systems
• 13.2 eBrain - A Digital Super-Computer with the HMC (KTH Sweden, CEA-LETI, Linkoping U.)
• 13.3 CB-RAM Cross-Bar Device Model for Hybrid Design with SRAM/DRAM (NanyangTU)
• 13.4 3D TSV-based 3D-SRAM for High Performance Platforms (NTHU, ITRI,Fukuoka Inst.)
• 13.5 3D Stacking vs. 2D for multi-core architectures with DRAM (CEA-LETI, MINATEC)
• 13.6 Waveform Capture with 100 GB/b I/O, 4k TSV and Active Si Interposer (KobeU, ASAET)
• 13.7 Improving QoS Using 3D-DRAM and External DRAM (U. of Calif.Irvine, George Mason U.)

14.0 Interface IO for 3D DRAM Subsystems

• 14.1 Overview of Interface I/O for 3D DRAM Systems
• 14.2 Pulse Amplitude Modulation Memory IO for 3D Stacked DRAMs (West Virginia U.)
• 14.3 Inductive Coupling for 3D Integration in a SiP (Keio U, Carnegie Mellon U, NII Tokyo)

Bibliography

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