MEMORY STRATEGIES INTERNATIONAL Semiconductor Memory Services
| Home | Reports | Seminars | Consulting | Contact Us | About Us | See Our Memory Technology Reports on: 3D TSV DRAM | 3D NAND Flash | 3D ReRAM/Cross Point Array | Gate All Around | Embedded Flash | Resistance RAM | Embedded DRAM | MRAM | Ferroelectric | Nanocrystal Flash |

Contents | Purchase

A Memory Strategies Focus Report

RRAM, Selector & 3D Cross-Point Array Technology, February 2016
 

3D cross-point Resistance RAM (RRAM) arrays have the potential to be the next high density non-volatile memory potentially succeeding the NAND Flash. Near term applications being considered include: Storage Class Memory, mobile device storage, medical devices and IoT memory. RRAM cross-point array memories are compatible with advanced CMOS production processes with minimal added mask and process steps. Peripheral circuits can be placed under the array to increase array efficiency. Fabrication techniques, such as used for 3D vertical NAND flash, can be used to increase the density of a vertical 3D RRAM cross-point array at low cost and 4F2 cell size. Stack height can be reduced using ultra-thin layers, possibly of graphene. Sneak current leakage in high density arrays can be reduced by using RRAMs with highly non-linear IV curves, by using one of the many bidirectional selectors in development or by the use of anti-serially connected bipolar RRAMs, "complementary resistive switches", for the memory element in a cross-point array. A significant number of models have been developed and many test and reliability studies conducted in the past year in preparation for this high density memory technology entering production. A complete bibliography of the 260+ research papers on this topic covered in this report is included for ease of reference.

Overview | Purchase

Table of Contents -  RRAM, Selector and 3D Cross-Point Array Technology, February 2016

Executive Summary

1.0 Overview and Applications

• 1.1 Overview of 3D Cross-Point Array Memory
• 1.2 Storage Class Memory
  • 1.2.1 Overview of Storage Class Memory (Micron)
  • 1.2.2 Categorizing of MLC Storage Class Memory Using Two Types of RRAM (NCTU)
  • 1.2.3 Solid State Storage Using ReRAM and 3-bpc MLC NAND (U. Tokyo, Chuo U.)
  • 1.2.4 Issues for Using RRAM for Storage Class Memory (Politechnico di Milano)
  • 1.2.5 Vertical 3D 64Gb RRAM for Dense & Read Intensive Storage (Penn St, Arizona St.)
  • 1.2.6 CB-RRAM Cross-Point Array for Use in Storage Class Memory (Micron, Sony)
  • 1.2.7 Hybrid SS Storage System with SCM & NAND Flash for Big Data Application (ChuoU)
• 1.3 RRAMs in Big Data Applications
  • 1.3.1 256bit Wordlength 2.5T1R ReRAM TCAM in CMOS Logic (NTHU, TSMC, NCTU)
  • 1.3.2 3T1R nvTCAM Using MLC ReRAM with <1 ns Search Time (NTHU, ITRU, NCTU)
  • 1.3.3 4T2R ReRAM in TCAM for Big Data Processing (NTHU, NCTU, NDL, ITRI)
  • 1.3.4 RRAM Crossbar Array for Matrix Vector Multiplication (Tsinghua U, Arizona SU)
  • 1.3.5 Hybrid Cloud Storage of RRAM & TLC NAND Flash with RAID-56(Chuo U, UofTokyo)
  • 1.3.6 ReRAM Cross-bar Array Memory System Characteristics (Oakridge National Lab.)
• 1.4 RRAMs in Neuromorphic Systems
  • 1.4.1 Overview of Neuromorphic Systems
  • 1.4.2 HfO2 RRAMs as Synapses for Convolutional Neural Networks (CEA-LETI)
  • 1.4.3 Neuromorphic Pattern Learning using ReRAM Electronic Synapse (NCTU)
  • 1.4.4 3D Synaptic Device using a Ultralow Energy ReRAM (NCTU)
  • 1.4.5 ReRAM Cross-point Array for Parallel Dictionary Learning (Arizona State U.)
  • 1.4.6 Suppressing Intrinsic Variations in Metal-Oxide Synaptic RRAMS (Peking U.)
  • 1.4.7 3-D Vertical Analog Switching RRAM for Neuromorphic Computing (U. of Michigan)
  • 1.4.8 RRAM Synaptic Device for Neuromorphic Computing (Postech, Gwangju IST)
  • 1.4.9 RRAM for Binary and Analog Synapses in Neuromorphic Computing (ASU)
  • 1.4.10 Neural Networks Using Resistive Memory (CEA-LETI, CEA-LIST, INRIA)
  • 1.4.11 Two-Terminal Resistive Devices for Neuromorphic Computing (ASU, Stanford, U. of Penn.)
• 1.5 Ultra-Low Power Circuits and Systems (Internet of Things)
  • 1.5.1 OxRAM Pulse Latch in nvFF for IOT Low Standby Power Circuit (U. Grenoble Alpes)
  • 1.5.2 Low Power Level-Shifter Using eRRAM Macro (NTHU, NCHU, ITRI)
  • 1.5.3 ReRAM in Ultra-Low Power Systems (CEA-LETI, Minatec)
• 1.6 ReRAM in Logic and FPGAs
  • 1.6.1 Normally-off Logic Using Resistive Switches for Instant-On Circuits (Politic. di Milano)
  • 1.6.2 Low Power FPGA Using Integrated RRAMs (Swiss Federal IT)
  • 1.6.3 Low Power Near-Vt RRAM-Based FPGA (EPFL)
  • 1.6.4 nvLUT with ReRAM for Reconfigurable Logic (ITRI, Nat. Taipei U., NTHU, Min Shin U.)
• 1.7 A Temperature Sensing RRAM Architecture for 3-D IC's
• 1.8 ReRAM for Physical Unclonable Function (PUF)
  • 1.8.1 Overview of ReRAM Physical Unclonable Function (PUF)
  • 1.8.2 RRAM-based PUF for Hardware Security (TD Research, GlobalFoundries)
  • 1.8.3 RRAM Cross-Point Array PUF using four cell selection (Arizona State U.)
  • 1.8.4 Reconfigurable PUF Using Resistive Variability (Global Foundries)
• 1.9 RRAMs for Space Applications
  • 1.9.1 Low Temp Switching of Pt/HfOx/TiN RRAM for Aerospace (Arizona State U)
  • 1.9.2 RRAMs for Space Applications (Aerospace Corp.)
• 1.10 Random Number Generator Based on RRAM (Politecnico di Milano)
• 1.11 Circuits Using Embedded ReRAM
  • 1.11.1 Overview of Logic Circuits with Embedded ReRAM
  • 1.11.2 nvMCU with 65 nm eReRAM for NV Processing (Tsinghua U., NTHU, U. of Calif.LA)
  • 1.11.3 Multistate Register Using RRAM (U. of Rochester, Technion-Israel IT)
  • 1.11.4 Single RRAM nvSRAM for Reduced Store/Restore Energy (NTHU, NDL, NCHU, EOL ITRI)
  • 1.11.5 ReRAMs Optimized for FPGA and for nvFF (CEA, LETI)
  • 1.11.6 ReRAM based Non-Volatile Flip-Flops for Low Voltage SoCs (EPFL)
• 1.12 Analysis of Production ReRAM Devices
  • 1.12.1 Analysis of 8-bit MCU with 64kB of embedded TaOx ReRAM (Jet Propulsion Lab)

2.0 RRAM Chips - Device and Circuitry

• 2.1 Overview of ReRAM Device and Circuits
• 2.2 Embedded RRAM Chips - Device and Circuitry
  • 2.2.1 Sense Amp and Write Termination Method for eRRAM Macro (NTHU, TSMC)
  • 2.2.2 2T2M Memristor Cell for Stable RRAM Modules (Nile U., AinShams U., Cairo U.)
  • 2.2.3 Read Circuits for Scaled ReRAM (NTHU, Nat Chung Hsin U., I-shou U., ITRI, NDL)
  • 2.2.4 Chip Level Characterization of 28 nm Embedded RRAM (STMicro, CEA LETI, U. de Lyon)
  • 2.2.5 65 nm 2 Mb ReRAM Macro with Vertical Parasitic BJT Switches (NTHU, ITRI, TSMC)
  • 2.2.6 CMOS 28 nm 1Mb ReRAM 0.27 - 1V READ (Nat. Tsing Hua U, TSMC)
• 2.3 High Density RRAM Chips - Device and Circuitry
  • 2.3.1 Sensing Circuit Improve Sense Margin in Scaled RRAM (Yonsei U., Qualcomm)
  • 2.3.2 130 mm2 24 nm 2-layer 32Gb ReRAM Cross-point Array ReRAM (SanDisk, Toshiba)

3.0 RRAM Cell and Cross-point Array Chip - Process and Manufacturing

• 3.1 Overview of Cross-Point Array Process and Manufacturing
• 3.2 A Low Cost Manufacturable 16 nm FINFet RRAM Logic Process (NTHU, TSMC)
• 3.3 3D Vertical Structure for 1TnR Non-linear RRAM (ITRI MingShin UofS&T, NTHU)
• 3.4 Ultrathin 2nm Thick HfOx-based RRAM with 3D Integration (Stanford U.)
• 3.5 A Manufacturable HfO2/Ti-based Vertical RRAM (CEA LETI)
• 3.6 Modeling the Metal Ox RRAM Forming Process Using Stochastic Simulation(Peking U.)
• 3.7 HfOx RRAM for Cross-Point Wafer Scale Memory (POSTECH, Sungkyunkwan U)
• 3.8 Logic Compatible 28nm Via Diode in Cu BEOL for 3D RRAM (NTHU, TSMC, ITRI)
• 3.9 Scaling HfOx-Based VRRAM for 3D Cross-Point Architecture (PekingU, Stanford U., ASU)
• 3.10 Eliminating the Forming Process Using N-AlOx RRAM (IBM, Stanford)
• 3.11 Stack Engineering of RRAM to Improve Performance (Tsinghua Univ.)
• 3.12 Fabless Manufacture of Nano-pillar SiOx RRAM+Diode (U of Texas, NCTU, Sun Yat-SenU)
• 3.13 Tri-Resistive Switching of H Induced RRAM (NSYSU, PekingU. TFDI, NKN, ROC, NCTU)
• 3.14 28 nm 1R1D Cross-Point Array in CMOS Compatible Process (TSMC, ITRI)
• 3.15 Double Layer 3D Vertical ReRAM for High Density Arrays(NCTU, TNNL, Winbond)
• 3.16 Study of Cell Performance for Different Stacked RRAM Geometries

4.0 An Analytical Look at Vertical Cross-Point Memory Array Design

• 4.1 Introduction to the Theory of Cross-Point Arrays and 3D Resistive Arrays
• 4.2 Physics-based SPICE model of HfOx-based RRAM (Peking U., Stanford U.)
• 4.3 3D BiCS RRAM Using 30 nm Graphene Plane Electrode (Stanford Univ.)
• 4.4 3D RRAM Benchmark with 3D NAND Flash (Arizona State U.)
• 4.5 Various Models of Resistive Switching Devices (Aachen U., Peter Grunberg Institut)
• 4.6 Design Optimization of Vertical RRAM for 3D Cross-Point Array (Peking U)
• 4.7 Design Guidelines for 3D RRAM Vertical Cross-Point Arrays (ASU, PekingU, StanfordU)
• 4.8 SPICE Model with Intrinsic Variation for RRAM Analysis (PekingU, StanfordU, ArizonaU)
• 4.9 Analysis of Pulse Rise Time During Write in Cross-Point Array (Stanford, Arizona State U)
• 4.10 3D VRRAM Using Horizontal Electrodes - BiCS Concept (ITRI, MingShin U of S&T)
• 4.11 Cost Advantage of 3D Horizontal ReRAM Compared to 3D Vertical ReRAM
• 4.12 3D Vertical RRAM Cross-Point Array Scaling Limits (Stanford U, IME Peking U.)
• 4.13 Cross-Point Array Model for Line Resistance&NonLinear Devices (GlobalFoundries)

5.0 Selectorless and Reduced Selector Cross-Point Memory Arrays

• 5.1 Selectorless Cross-Point RRAM Arrays
  • 5.1.1 Overview of Vertical Selectorless Cross-Point Arrays
  • 5.1.2 A Cross-Point MLC ReRAM with Sneak Current Compensation(Sungkyunwan U, Samsung)
  • 5.1.3 Low Voltage READ/WRITE for Selectorless ReRAM Array (EPFL, CSEM)
  • 5.1.4 Read-out Limits of linear selectorless RRAM Arrays (U.Southhampton, Imp. Col. London)
  • 5.1.5 3D Interweaved Selectorless Cross-Point Array RRAM (NTHU, TSMC)
  • 5.1.6 3D Vertical AlOd/Ta2O5-x/TaOy RRAM (Tsinghua University)
• 5.2 1TnR Cross-Point Vertical RRAM Arrays
  • 5.2.1 Overview of 1TnR Vertical RRAM Arrays
  • 5.2.2. 1TnR Array Architecture Using Carbon Nanotube FET Selector.
  • 5.2.3 1TNR Array Architecture for High Density Cross-Point Arrays (Stanford)
  • 5.2.4 Vertical 1TnR RRAM Cross-Point Array Operation(Peking U. StanfordU, Arizona St. U)
  • 5.2.5 Analysis of Device Characteristics of 3D Vertical RRAM Cross-point Array (ASU)
  • 5.2.6 Effect of LRS Non-Linearity on Sense Margin In A 3D Vertical Array (ITRI)
  • 5.2.7 Analysis of Vertical Cross-Point RRAM (VRRAM) (IMEC, KULeuven, ESAT)
• 5.3 Non-Linear and Self-Rectifying Cross-Point Arrays
  • 5.3.1 OverView of Non-Linear and Self-Rectifying Cross-Point Arrays
  • 5.3.2 Forming-Free, Self-Rectifying Analog Resistance Memory (IMEC, KU Leuven)
  • 5.3.3 TiOx-based Tunnel Barrier Effects in HfO2 Switching MO-RRAM (POSTECH)
  • 5.3.4 TiN/Ti/HfOx/TiN RRAM Integrated in 180 nm CMOS (Nat. Tsing Hua U.)
  • 5.3.5 Conduction Mechanisms of Self-Rectifying HfO2 RRAMS(Fudan U, Nanyang TU, SUSTC)
  • 5.3.6 Self-Rectifying Bipolar ReRAM Using Schottky Barrier (NCTU, Winbond)

6.0 Characteristics of Various Bipolar Metal Oxide RRAMs

• 6.1 Overview of Metal Oxide RRAM Characteristics
• 6.2 MLC HRS Control in TiN/HfOx/Pt RRAM (Nanyang, IME, U. ES&T, IME, A*STAR)
• 6.3 Finding an Optimal ON/OFF Resistance Ratio for A 1D1R RRAM (IMEC)
• 6.4 Analysis of Cerium Oxide Bipolar RRAM (U.Texas Austin)
• 6.5 ITO RRAM Stop Voltage&I Compliance(NSYU, CHPC, NCTU, XiamenU, TSMC, XideanU)
• 6.6 Triple Ion Effect in GeSO RRAM (XidianU, NSYSU., China Nt. Pet. Corp, Xiamen U., NTHU)
• 6.7 Vertical Thin Film RRAM/Selector for High Density Arrays (NARL, NNDL)
• 6.8 Low Power 3-bit MLC TaOx RRAM (Pohang U. of S&T)
• 6.9 Resistive Switching Uniformity of Al/Zn/Sn/O and HfO2 Bilayer (NCTU)
• 6.10 Gate Voltage Ramp Programming for 1T1R RRAM (IME CAS, Tianjin U.)
• 6.11 Effect of Nb as an Oxygen Exchange Layer in HrO2 RRAM (Australian Nat. Univ.)
• 6.12 Electroforming Mechanism in Metal Oxide RRAMs (Inst. of Microelec, ICSICT)
• 6.13 Self-Compliance SET Switching with I-Current Sweep (A*STAR)
• 6.14 High Temperature Retention in ZrO2 RRAM with Thin ZnO Layer(NCTU)
• 6.15 Functionality of Multibit 1T1R RRAM Arrays (Boston U.)
• 6.16 Multi-Bit Switching in Bipolar RRAM Using Combined Operations (Tsinghua U.)
• 6.17 Bipolar TiOx/TaOx RRAM Using NbO2-based Selector (SK Hynix, HP)
• 6.18 Various Models of Switching Mechanisms in Oxide-Based RRAMs (ASU)
• 6.19 AlOx Interfacial Layer in W/AlOx/TaOx/TiN RRAM (Chang Gung U, Nat. TaiwanU)
• 6.20 Switching of TaOx/TaON Using Ionic Control of Carrier Tunneling (Hanyang U)
• 6.21 RTN & Current Compliance in HfO2 RRAM in the HRS (U.di Modena e Reggio Emilia)
• 6.22 Resistive Switching Processes of AlOx/WOy Bilayer RRAM (Tsinghua U.)
• 6.23 Compact Model for Bipolar Oxide RRAM (IM2NP, Aix-Marseille U., CIA-Leti, MINATEC)
• 6.24 RRAM with Low SET, RESET V and CC (U. Tokyo, GlobalFoundries, A*STAR, SUS&T)
• 6.25 Filamentary Metal Oxide RRAM with Inserted Layer (Postech, Gwanju)
• 6.26 Nanobattery Effect on RRAM Stability&Endurance (Julich Aachen., Peter Grunberg Inst.)
• 6.27 Switching Speed Improvement of Ta2O5/AlOä/TaOy Trilayer RRAM (Tsinghua U)

7.0 Material, Thermal, and Reliability Characteristics of MO RRAMS

• 7.1 Overview of Material, Thermal and Reliability Characteristics of MO RRAMS
• 7.2 Cycling Degradation of HfOx RRAM ( DIEB, Politec.di Milano, IU.NET, Micron)
• 7.3 Surface Roughness on ZnO RRAM( King Abdullah U. S&T, Nat. TaiwanU., KyotoU, PurdueU,)
• 7.4 Programming to Suppress Retention Tails in OX-RRAMS (IMEC, KU Leuven)
• 7.5 Program-Verify Algorithm for Multi-bit HfO2 RRAM Operation (U M. e R. Emilia)
• 7.6 Thermomic Measurements on Filamentary RRAM (Technion-Israel IT, Carnegie Mellon)
• 7.7 Tailing of Resistive State Distributions in HfOx and TaOx RRAM (IMEC, U. Antwerp)
• 7.8 Compact Model of Bipolar RRAM Cells (NCKU, Chroma ATE, EDACPOWER Elec)
• 7.9 An Optimized TiN/TaOx/HfO2/TiN RRAM (Tsinghua U., Rambus)
• 7.10 Characteristics and Variability for a MLC HfOx RRAM (Pohang U. of S&T)
• 7.11 Model of Read Disturb Mechanism in HfOx RRAM (Singapore U. of T&D, A*STAR)
• 7.12 Pulsed Cycling Variability and Endurance in HfOx RRAM (Polit. de Milano, Micron)
• 7.13 Data Retention Study in HfO2 RRAMs (DIEB, Politec. de Milano, IU.NET)
• 7.14 Gamma Irradiation Effects on TiN/HiOx/Pt RRAM (Tsinghua U.)
• 7.15 WO RRAM Cycling SET-Disturb Failure Time Degradation (NCTU, NNDL, Macronix)
• 7.16 LRS Retention in HfO2& HfAlO RRAM (CEA, LETI, MINATEC, STmicro, Stanford U.)
• 7.17 Improving RRAM Endurance by Using A Soft Forming Algorithm (Fudan U., SMIC)
• 7.18 Contact Resistance Reduction for MoS2FETs (GIST, Incheon Nat. Univ.)
• 7.19 MO-RRAM with Control of Capacitive Surge Current During Write (Rambus)
• 7.20 Scaling the Conductive Filaments of Oxide-Based ReRAM (Politec. di Milano)
• 7.21 OxRRAM ON/OFF Resistance Analysis vs. Circuit Variability (IM2NP, Aix-Marseille U.)
• 7.22 Reducing Thermal Effect in RRAM Switching by Optimizing Uniformity (Peking U.)
• 7.23 Resistive Switching Enhancement of HfO2 Thin Film by Zn Doping (FudanU.)
• 7.24 Low Frequency Noise in n+Si-HfO2-No RRAM (Fudan University)
• 7.25 Thermal Stability of Low-Voltage TaOx RRAM (A*STAR, Univ. Cambridge)
• 7.26 Effect of Ti Capping Layer on HfOx-based RRAM Performance (A*STAR, Stanford)
• 7.27 Oxygen Effect in InO on RRAM Switching (NSY-SU, NCKU, NCTU, ITRU, Xiamen U)
• 7.28 Statistical Fluctuations in HfOx RRAM for SET/RESET (Polit.di Milano, Micron)
• 7.29 Model for Estimating Conductive Filament Characteristics in RRAM (Panasonic)
• 7.30 Electrode Type Effect on Filament Characteristics in HfO2 RRAM(CEA-LETI, Stanford)
• 7.31 Forming Energy Role in Reliable RRAM Operation (NIST, SEMATECH, Old Dom.U)
• 7.32 Stochastic Modeling of SET and RESET In RRAM Stacks (SUTD, MIT, A*STAR)
• 7.33 RTN and Cycling Variability in HfO2 RRAMs (U. di Modena e Reggio Emilia)
• 7.34 Oxygen Accumulation Effect on Resistive Switching for Gd:SiO2 RRAM (Peking U., NSYSU., NCKU., U.of Texas, Tung Fang Design U., N. Kaohsiung Normal U., NCTU)
• 7.35 Switching and Reliability Mechanisms for ReRAM (Panasonic)
• 7.36 Modeling Switching in Binary Metal Oxides (Stanford, KanagawaIT, U Tsukuba, Nagoya U)
• 7.37 Effect of ALD Temperature of HfOx RRAM Switching Properties (U. of Southampton)
• 7.38 Hf1-xAlxOy Amorphous Dielectrics for High Performance RRAMs (IMEC)
• 7.39 Effect of Metal Electrodes on Switching Voltage in NiO RRAM (U. of Elec. S&T)
• 7.40 Process Effects on Switching of Al/HfOx/ITO Memories (Zhejiang Normal U.)
• 7.41 Switching Behavior of W/TiN Contact in an MO-RRAM (Chang Gung U.)
• 7.42 Effect of SET Temperature on HfO2 RRAM Retention (CEA-LETI, STM, Aix MarceilleU)
• 7.43 Electrical Property Temperature Dependence of HfOx-based RRAM (Stanford U, IBM)
• 7.44 RRAM Heat Dissipation Mechanisms Simulated & Experimental (Technion-Israel IT)
• 7.45 Study of Variability of the LRS in a Ni/HfO2 based RRAM (CNM-CSIC)
• 7.46 Defects-Trapping TaOx/HfOx/HfOx ReRAM (ITRI, MinghsinU)

• 8.1 Overview of Conductive Bridge RAM Characteristics
• 8.2 Single Event Susceptibility in CB-RAM (Arizona State U.)
• 8.3 Method for Tightening Vset and Vreset Distributions of CB-RAM (Virginia Polytech)
• 8.4 Operating Current Dependence of Cu Mobility in CB-RAM (KU Leuven, IMEC)
• 8.5 CB-RAM with High ON/OFF Resistance Ratio (Crossbar)
• 8.6 SET and RESET for MLC CB-RAM for High Density Storage (IME CAS)
• 8.7 10nm Cu Electrode Subtractive Dry-Etch Patterning for CB-RAM (IMEC, Tokyo Electron)
• 8.8 CB-RAM Quantized Conductance Effect (Aachen U. Peter Grunberg I., U. Coll. London)
• 8.9 Bilayer M-O CB-RAM for Improved Window Margin and Reliability (CEA LETI)
• 8.10 CB-RAM Variability Caused by Multiple CF (IMEC, KU Leuven, U.Gent)
• 8.11 Effect of VOx Layer added to Cu/HgOx/TiN CB-RAM Cell (Tianjin U.)
• 8.12 Better Retention of LRS in CB-RAM with Single Filament Formation (IME, CAS)
• 8.13 Single Event Induced Soft Errors in PMC(CB-RAM) Memories (Arizona State U.)
• 8.14 Effect of SET/RESET on CB-RRAM High Temp Data Retention (CEA-LETI)
• 8.15 Model of ECM (CB-RAM) cells (Forschungszentrum Julich, JARA)
• 8.16 Origin of Deep RESET and Low Variability of Pulse-Write CB-RAM (IMEC)
• 8.17 Performance Comparison of OxRAM and CB-RAM Arrays (Micron)
• 8.18 Gate Induced Resistive Switching in 1T1R CB-RAM (Chinese Academy of Sciences)
• 8.19 A Compact Model for Conductive Bridge RAMs (CEA-LETI, Aix-Marseille Univ.)
• 8.20 CB-RAM Cross-Bar Device Model for Hybrid Design with SRAM/DRAM (NanyangTU)
• 8.21 CB-RAM Bit-Error Rate from Ionizing Radiation (Arizona State U., Adesto Tech)

• 10.1 Overview of Unipolar RRAM in Cross-Point Arrays
• 10.2 Unipolar ReRAM and MLC Switching in TiW/SiOx/TiW (UTexas Austin, PrivaTran)
• 10.3 Variability of the LRS of Ni/HfO2 Unipolar RRAMs (U. Autonoma de Barcelona)

• 11.1 Overview of Characterization, Test, Reliability and Modeling of RRAM Arrays
• 11.2 HfO2 Dielectric RRAMs
  • 11.2.1 Resistance Instability in HfO2 RRAM (IMEC, U of Pavia, KU Leuven)
  • 11.2.2 RRAM Array Form/Switch Variability (UFerrara, IHP Micro, UABarcelona, KievPy, Nplust)
  • 11.2.3 Endurance Failure Model for Filamentary RRAM (IMEC, U. of Calabria)
  • 11.2.4 Model Linking ReRAM IV Characteristics with Material Microstructure (IME CAS)
  • 11.2.5 Characterization of Temperature Impact on RESET Operation (U. of Modena)
  • 11.2.6 RRAM Defect Modeling and Failure Analysis Test (National Tsing Hua U.)
  • 11.2.7 Modeling of Radiation Induced Changes in HfO2 1T1R RRAM
  • 11.2.8 Effect of Radiation on 1T1R HfO RRAM (Vanderbilt University)
  • 11.2.9 Pulse-Train Measurements Techniques for RRAMs (Stanford U)
  • 11.2.10 Radiation Hardness of HfO2 RRAM to EUV and X-ray (NCTU, NSRRC, ITRI)
  • 11.2.11 Model for Voltage Dependent RTN in HfOx RRAM (Politecnico di Milano)
  • 11.2.12 RTN Noise Amplitude in HfO RRAMs (NCTU, Nat. Nano-Device Lab)
  • 11.2.13 Effect of RESET Current Overshoot on RRAM Reliability (Pohang University)
  • 11.2.14 Lateral and Vertical Scaling Effect on Reliability of Metal Oxide RRAMs (IMEC)
  • 11.2.15 Write Disturb Analysis of Cross-Point RRAM (PekingU, StanfordU, Arizona St.U)
• 11.3 TaOx Dielectric ReRAMs
  • 11.3.1 ReRAM Retention Prediction Based on 3D Filament Structure (Panasonic, Kyoto U.)
  • 11.3.2 Cross-Point ReRAM Model with Reliability & Variability (Penn St., U. Calif. SB)
  • 11.3.3 Impact of Programming Pulses on Endurance of Scaled Ta2O5 ReRAMs (IMEC)
  • 11.3.4 Effect of Single Event Upsets on MCU with eReRAM ( NASA Goddard SFC)
  • 11.3.5 Ta Scavenger Electrode in Switching&Reliability of TiN/Ta2O5/Ta RRAM (IMEC)
• 11.4 Stochastic Dif. Equation & Percolation Hopping Model for RRAM (Panasonic,Kyoto U)
• 11.5 Effect of Narrow Conductive Filaments During Forming (Univ. di Ferrara, Univ.
• 11.6 SPICE Model Capturing Device Features of RRAM for System Design (Stanford U.)
• 11.7 Modeling of Multiferroic BiFeO3 Structures (Univ. Autonoma de Barcelona)
• 11.8 Modeling OxRAM Variability Low-to-High Resistance (CEA LETI, IMEP-LAHC, STMicro)
• 11.9 Effect of Low Frequency Noise of Read Distribution of ReRAM (Politec. di Milano)
• 11.10 Noise Types in an ReRAM Due to Trapping and Oxygen Migration {NCTU, ITRI)
• 11.11 Effect of Pulse Program Conditions on Endurance of RRAM (Tianjin U.)
• 11.12 ReRAM Cross-Point Array Power Dissipation. (Ewha Univ., SK Hynix)
• 11.13 Asymmetric Write Algorithm without Verify (Fudan U., SMIC)
• 11.14 Assessing Write-Disturb Tolerant 3D VRRAM Arrays (Peking U., Stanford U, ASU)
• 11.15 Characterization 1T1R 4K RRAM (U. di Ferrara, HP, T U. Berlin, Brandenburg TU., IASA)

• 12.1 Overview of Experimental and Future RRAMs
• 12.2 Temperature Dependence of Magnetoresistance of ON State of RRAM (Kansai U.)
• 12.3 CMOS Compatible TiN RRAMs (A*STAR, Peking Univ., Stanford)
• 12.4 Ga-Doped ZnO Nanrod Thin Film RRAM for Transparent Application (NCTU)
• 12.5 TiOx/Al2O3/TiO2 RRAM with Graphene Electrodes (U of Texas:Dallas, Georgia IT)
• 12.6 GeTe/Sb2Te Super-Lattice Topological Switching RAM (TRAM) (LEAP, U. of Tsukuba)
• 12.7 Effect of CNT RRAM Scaling on Retention and ON/OFF Ratio (Nantero, Cisco Sys.)
• 12.8 Electromechanical Diode for a Cross-Point NV Memory( CEA-Leti, Sumsung, U. of Calif.)

• 13.1 Overview of Bidirectional Selector/Drivers for Cross-Bar Arrays
• 13.2 Metal Oxide Selectors
  • 13.2.1 Cu BEOL Compatible HfO2 Diode Selector with Ultra Low off-current (IME CAS)
  • 13.2.2 1S1R ReRAM Using NbO2 Selector in 4F2 2x nm Technology (SK Hynix, HP Labs)
  • 13.2.3 AlOx Selector for Crossbar RRAM with Resistive & Threshold Switching (IMECAS)
• 13.3 Chalcogenide Selectors
  • 13.3.1 Doped Chalcogenide Selector for Ultralow Holding Voltage RRAM (A*STAR)
• 13.4 MSM Selector Diodes
  • 13.4.1 Tunneling MSM Diode Selector for Large Drive Current and Nonlinearity (IMEC)
  • 13.4.2 CMOS Comp. Metal/a-Silicon/Metal(MSM) Diode for Bipolar ReRAM (IMEC)
• 13.5 MIM Selectors
  • 13.5.1 Dynamic Power of MIM vs. NPN Selectors in Bipolar RRAM Arrays (IIT Bombay)
• 13.6 Schottky Diode Selectors for Bipolar RRAM
  • 13.6.1 Schottky Diode Selectors for Bipolar-Type RRAM (Lanzhou U.)
• 13.7 Tunnel Diode Selectors for Bidirectional Switches
  • 13.7.1 Scaled Tunnel Barrier Selector with Current Density > 10⁷A/cm2 (POSTECH)
  • 13.7.2 MultiLayered Tunnel Oxide Selector for Cross-Point RRAM (Postech)
  • 13.7.3 Multilayered Tunnel Oxide Selectors for Bipolar RRAMs (Pohang U)
  • 13.7.4 Fast MIM Tunnel Diode Selectors for Bidirectional Switches (IMEC, KU Leuven)
• 13.8 MIEC Selection Devices for Bidirectional Switches
  • 13.8.1 MIEC BiDirectional Complementary Atom Selector Switch (Postech, Gwangju IST)
• 13.9 Threshold Switching IMT Select Devices using V or Nb
  • 13.9.1 IMT Bidirectional Selector Devices for Bipolar RRAMs (Pohang U)
  • 13.9.2 NbO2 Threshold Switching Selector for 3-D Cross-Point RRAM (Postech)
  • 13.9.3 Confined NbO2 as a Selector in Bipolar ReRAMS
  • 13.9.4 Threshold Switching AsTeGeSiN Select Device (Samsung)
• 13.10 A Triangular Barrier NIPIN Selector for Bipolar RRAM (IIT, U. of Stuttgart)

• 15.1 Overview of Selector Design and Characterization
• 15.2 Read Issues in 1-Bidirectional Diode 1ReRAM Nanoscale CB arrays (U. of Toledo)
• 15.3 Benchmarks for Access Devices for ReRAM (IBM)
• 15.4 Speed-Power Analysis of RRAM Arrays with Selection Devices (Peking U)
• 15.5 Selector Requirements During Write for Cross-Point RRAM Arrays (U of Michigan)
• 15.6.Selector Requirements During Read for Cross-point Array RRAMs (U. of Michigan)
• 15.7 Selector Design for 1S1R RRAM Crossbar Array (IMEC)

Bibliography

Overview | Contents

To order "RRAM, Selector & 3D Cross-Point Array Technology, February 2016": 

Contact Memory Strategies or
Send us the information requested below by e-mail, fax, or post along with your check, bank transfer, or purchase order for $975. ($850 if a Memory Technology Report has been ordered from Memory Strategies in the past year.)

ORDER FORM: Please send ______ copies of  "RRAM, Selector & 3D Cross-Point Array Technology, February 2016" to:

Report Format

____ PDF. Will be sent by email. Please send your order by email, if possible. Printing hardcopy from PDF is permitted.

Submit Order and Payment Information via:
    Email: info@memorystrategies.com, or
    Fax:    +1 512 900 2846
    Post:
        Memory Strategies International,
        16900 Stockton Drive,
        Leander, Texas 78641, U.S.A.

To pay by:

• Credit Card: please fax credit card information to +1 512 900 2846
• Bank Transfer: please send in your order and request transfer details.
• Purchase Order: submit purchase order details with order.

For more information, please Contact Memory Strategies