Gate All Around Nanowire report

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3D Gate All Around Nanowire Memory, November 2013
(Charge Trapping Junctionless and Floating gate)

GAA Charge trapping SONOS nanowire memories have been explored extensively. Both horizontal and vertical SONOS memory strings have been explored along with those using high-k dielectrics and metal gate. Analytical models have been created and various parameters and issues explored. Both single crystal silicon and polysilicon nanowire memories have been discussed. Junctionless GAA charge trapping nanowire memories have been studied with both single crystal and polysilicon nanowires. Radial effects on reliability and endurance are discussed. Studies of cylindrical effects on charge trapping characteristics are reviewed. Horizontal nanowire memories. using single crystal silicon have been built and simulated. Silicided surround gates have been used. Vertical channel floating gate memory cells have been explored with separated control gates, dual control gates and with a sidewall control pillar. A cost analysis for 3D GAA NAND flash is discussed. 65+ pages.

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3D Gate All Around Nanowire Memory, November 2013

Table of Contents

Executive Summary

1 Overview/Introduction

2 Early Gate-All-Around (GAA) Nanowire Single Crystal SONOS Memories

2.1 Early GAA SONOS Memory using Silicon Nanowires (Samsung)
2.2 Vertically Stacked Silicon Nanowire GAA SONOS Memories (NUS, IME Singapore)
2.3 GAA CT NAND Flash String Using a Single Silicon Nanowire (Samsung)
2.4 Silicon Nanowire CT Memory with High-K Dielectric and Metal Gate (A*STAR, NUS)
2.5 Review of GAA NW Memories (A*STAR, IIT, Silterra)
2.6 High-k Dielectric and Metal Gate on GAA Si-NW CT Memory (A*STAR, NUS)
2.7 Semi-Analytical Model of GAA Charge Trap Memories (Politecnico di Milano, Micron)
2.8 Transient Vth Shift After Erase and Effect on CT GAA- Si-NW Devices (KAIST, Hynix)
2.8 NV Gate-All-Around Single Crystal Si Nanowire Memory on Bulk (Samsung, KAIST)
2.9 Gate-All-Around CT NW Memory with HfAlO trapping layer (National Chiao Tung U.)

3 Early GAA Polysilicon Charge Trapping Nanowire Memories

3.1 GAA Polysilicon Nanowire Charge Trapping NV Memory (A*STAR, NUS)
3.2 Early Gate-All-Around NW Memory Verification (NCTU, NNDL)
3.3 Rectangular Polysilicon Multiple Channel Nanowire CT TFT Memory (NCTU)
3.4 Polysilicon Hybrid Nitride-Nanocrystal GAA Charge Trap Memory (NCTU,NTHU)
3.5 Junctionless Polycrystalline GAA HfO2/Si3N4 TL Memory Storage (NTHU, NNDL)

4 Junctionless GAA Charge Trapping Nanowire Memories

4.1 Interface Traps in Silicon Nanowire MOSFET (Nanyang TU)
4.2 Junction-Less 3D Stacked SiNW SONOS(A*STAR, Nanyang U, Global Foundries)
4.3 Junctionless GAA SONOS Si NanoWire on Bulk for 3D Stack NAND (KAIST)
4.6 GAA SNW Junction-Less SONOS NAND(A*STAR,Nanyang,PekingU,GlobalFound.)
4.7 Erase Saturation in Cylindrical Junction-less CT Arrays (Politecnico di Milano, IFN-CNR)
4.8 Erase Constraint for 3D Junction-Less CT Memory Array (P. di Milano, CNR Milano)

5 3-D Stacked Single Crystalline Flash Horizontal Nanowire Memory

5.1 Stacked SONOS Crystal Nanowires with GAA (CEA-LETI, MINATEC, IMEP-LAHC )
5.2 Silicon Nanowire Stacked 3-D NAND Flash Process (Samsung, Seoul Nat. U.)
5.3 Electrical Layer Selection in BL Stacked 3-D NAND Array (Samsung, Seoul Nat. U)
5.4 3-D Stacked NAND Flash (STAR) 3-D TCAD Simulation (Seoul Nat. U., Samsung)
5.5 3D Single Crystal Channel Stacked Array NAND Flash (Samsung, Seoul Nat. U.)

6 Vertical Single Crystal GAA Charge Trapping Nanowire Flash Technology

6.1 Overview of Vertical Flash Using GAA SONOS Nanowire Technology
6.2 3D Flash Using GAA SONOS with Vertical Crystal Si Nanowire (A-Star)
6.4 Fabrication of Two Independent GAA FETs on a Vertical SiNW (A*STAR, U.of Calif.)

7 Vertical Stacked Polysilicon GAA Charge Trapping Memory

7.1 Multiple Vertical GAA Flash Cells With Polysilicon NW Channel (Toshiba)
7.2 SONS to SONONS Process in Vertical GAA Poly NW Channel (Toshiba)
7.3 Silicided Control Gate to Reduce RC for Vertical Channel NAND String (Toshiba)
7.4 Vth Shift Characteristics of Vertical GAA SONOS/TANOS NV (Seoul Nat. Univ.)
7.5 Poly Channel Vertical Flash for 3D SONOS NAND (IMEC, ASM, John Moores U.)
7.6 3D Vertical Pipe CT Low Resistance (CoSi) WL NAND Flash (Hynix)
7.7 Vertical Channel GAA CT 3D NAND Cell Compared to 2D Planar FG NAND (Hynix)
7.8 Read Sensing for Thin Body Vertical NAND (Stanford, Seoul NU)

8 3D Vertical Channel GAA Floating Gate Memory Cells

8.1 3-D Floating Gate Cell with Extended Sidewall Control Gate (Tohoku U.)
8.2 3-D FG NAND with Separated-Sidewall Control Gate (Tohoku U, Hynix)
8.3. 3-D FG NAND Flash With Dual Control Gates and Surrounding FG (Hynix)
8.4 3-D Vertical FG NAND with Sidewall Control Pillar (Tohoku U, Hynix)

9 Research on GAA and Nanowire

9.1 Graphene Channel NV Memory with Al2O3/HfOx/Al2O3 Storage Layer (Seoul U.)

10 Cost Analysis for 3D GAA NAND Flash (Schiltron)

Bibliography

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